公开(公告)号：US20140015023A1

公开(公告)日：2014-01-16

申请号：US14027528

申请日：2013-09-16

Applicant: Soitec

Inventor： Frederic Allibert ,  Gweltaz Gaudin ,  Fabrice Lallement ,  Didier Landru ,  Karine Landry ,  Carlos Mazure ,  Mohamad A. Shaheen

IPC: H01L31/0248

CPC classification number: H01L29/78603 ,  H01L29/32 ,  H01L29/7841 ,  H01L31/0248

Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.

Abstract translation: 本发明的实施例涉及包括基底晶片，绝缘层和顶部半导体层的基板，其中绝缘层至少包括电荷密度高于1010电荷/ cm 2的绝对值的区域。 本发明还涉及制造这种基材的方法。

公开(公告)号：US20240312831A1

公开(公告)日：2024-09-19

申请号：US18566474

申请日：2022-05-25

Applicant: SOITEC ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Alexis Drouin ,  Gweltaz Gaudin ,  Séverin Rouchier ,  Walter Schwarzenbach ,  Julie Widiez ,  Emmanuel Rolland

IPC: H01L21/762 ,  H01L21/04

CPC classification number: H01L21/76254 ,  H01L21/0445

Abstract: A method for producing a semiconductor structure comprises: a) provision of a monocrystalline silicon carbide donor substrate and a silicon carbide support substrate; b) production of a useful layer to be transferred, comprising—implanting light species in the donor substrate at a front face, so as to form a damage profile, the profile having a main peak of deep-level defects defining a buried brittle plane and a secondary peak of defects defining a damaged surface layer, and—removing the damaged surface layer by chemical etching and/or chemical mechanical polishing of the front face of the donor substrate, so as to form a new front surface of the donor substrate; c) assembly of donor substrate with the support substrate; and d) separation along the buried fragile plane, leading to the transfer of the useful layer onto the support substrate, so as to form the semiconductor structure.

公开(公告)号：US20240170284A1

公开(公告)日：2024-05-23

申请号：US18550044

申请日：2022-03-03

Applicant: Soitec

Inventor： Gweltaz Gaudin ,  Christophe Maleville ,  lonut Radu ,  Hugo Biard

IPC: H01L21/02 ,  C23C16/02 ,  C23C16/32 ,  C23C16/56 ,  H01L21/762

CPC classification number: H01L21/02529 ,  C23C16/0227 ,  C23C16/325 ,  C23C16/56 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/76254

Abstract: A method for producing a semiconductor structure, comprises: a) providing a temporary substrate made of graphite having a grain size of between 4 microns and 35 microns, a porosity of between 6 and 17%, and a coefficient of thermal expansion of between 4×10-6/° C. and 5×10-6/° C.; b) depositing, on a front face of the temporary substrate, a carrier layer made of polycrystalline silicon carbide having a thickness of between 10 microns and 200 microns, c) transferring a working layer made of monocrystalline silicon carbide to the carrier layer to form a composite structure, the transfer implementing bonding by molecular adhesion, d) forming an active layer on the working layer, e) and removing the temporary substrate to form the semiconductor structure, the structure including the active layer, the working layer and the carrier layer. A composite structure is obtained in an intermediate step of the production method.

公开(公告)号：US20220359293A1

公开(公告)日：2022-11-10

申请号：US17757797

申请日：2020-12-15

Applicant: Soitec

Inventor： Gweltaz Gaudin

IPC: H01L21/78

Abstract: The invention relates to a process for manufacturing a composite structure comprising a thin layer made of a first single-crystal material positioned on a support substrate. The process comprises: a step a) of providing a donor substrate (10) composed of the first single-crystal material having a front face (10a) and a back face (10b), a step b) of providing a support substrate (20) having a front face (20a), a back face (20b), an edge (20c) and a first alignment pattern (21) on one of said faces or on the edge, a step c) of heat treatment applied at least to the donor substrate (10), under a controlled atmosphere and at a temperature capable of bringing about a surface reorganization on at least one of the faces (10a, 10b) of said substrate (10), the surface reorganization giving rise to the formation of first steps (13) of nanometric amplitude, which are parallel to a first main axis (P1), a step d) of assembling the donor substrate (10) and the support substrate (20) comprising, before the substrates (10, 20) are brought into contact, an optical alignment, to better than ±0.1°, between a locating mark (12) indicating the first main axis (P1) on the donor substrate (10) and at least one alignment pattern (21, 22) of the support substrate (20), a step e) of transferring a thin layer (100) from the donor substrate (10) onto the support substrate (20).

公开(公告)号：US20200336127A1

公开(公告)日：2020-10-22

申请号：US16922758

申请日：2020-07-07

Applicant: Soitec

Inventor： Gweltaz Gaudin ,  Isabelle Huyet

IPC: H03H9/02 ,  H01L41/08

Abstract: A hybrid structure for a surface acoustic wave device comprises a useful layer of piezoelectric material having a free first surface and a second surface disposed on a support substrate that has a lower coefficient of thermal expansion than that of the useful layer. The hybrid structure further comprises a trapping layer disposed between the useful layer and the support substrate, and at least one functional interface of predetermined roughness between the useful layer and the trapping layer.

公开(公告)号：US09905531B2

公开(公告)日：2018-02-27

申请号：US14411741

申请日：2013-06-05

Applicant: Soitec

Inventor： Ionut Radu ,  Marcel Broekaart ,  Arnaud Castex ,  Gweltaz Gaudin ,  Gregory Riou

IPC: H01L23/00 ,  H01L21/18 ,  H01L21/306 ,  H01L21/66

CPC classification number: H01L24/83 ,  H01L21/187 ,  H01L21/30604 ,  H01L21/30625 ,  H01L22/12 ,  H01L23/562 ,  H01L24/32 ,  H01L2224/29124 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29176 ,  H01L2224/2918 ,  H01L2224/29181 ,  H01L2224/29184 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83895 ,  H01L2924/01014 ,  H01L2924/0504 ,  H01L2924/10253 ,  H01L2924/201 ,  Y10T428/12493 ,  Y10T428/12639 ,  Y10T428/12646 ,  Y10T428/12653 ,  Y10T428/12674

Abstract: Method for producing a composite structure comprising the direct bonding of at least one first wafer with a second wafer, and comprising a step of initiating the propagation of a bonding wave, where the bonding interface between the first and second wafers after the propagation of the bonding wave has a bonding energy of less than or equal to 0.7 J/m2. The step of initiating the propagation of the bonding wave is performed under one or more of the following conditions: placement of the wafers in an environment at a pressure of less than 20 mbar and/or application to one of the two wafers of a mechanical pressure of between 0.1 MPa and 33.3 MPa. The method further comprises, after the step of initiating the propagation of a bonding wave, a step of determining the level of stress induced during bonding of the two wafers, the level of stress being determined on the basis of a stress parameter Ct calculated using the formula Ct=Rc/Ep, where: Rc corresponds to the radius of curvature (in km) of the two-wafer assembly and Ep corresponds to the thickness (in μm) of the two-wafer assembly. The method further comprises a step of validating the bonding when the level of stress Ct determined is greater than or equal to 0.07.

公开(公告)号：US09330958B2

公开(公告)日：2016-05-03

申请号：US14360124

申请日：2012-11-21

Applicant: Soitec

Inventor： Gweltaz Gaudin

IPC: H01L21/30 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/324

CPC classification number: H01L21/76251 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/26513 ,  H01L21/30625 ,  H01L21/324 ,  H01L21/76254

Abstract: The invention relates to a process for fabricating a heterostructure comprising at least one thin layer and a carrier substrate made of a semiconductor, the process comprising: bonding a first substrate made of a single-crystal first material, the first substrate comprising a superficial layer made of a polycrystalline second material, to a second substrate so that a bonding interface is created between the polycrystalline layer and the second substrate; removing from the free surface of one of the substrates, called the donor substrate, a thickness thereof so that only a thin layer is preserved; generating a layer of amorphous semiconductor material between the first substrate and the bonding interface by amorphization of the layer of polycrystalline material; and crystallizing the layer of amorphous semiconductor material, the newly crystallized layer having the same orientation as the adjacent first substrate.

Abstract translation: 本发明涉及一种用于制造异质结构的方法，该方法包括由半导体制成的至少一个薄层和载体衬底，所述方法包括：将由单晶第一材料制成的第一衬底接合，所述第一衬底包括形成的表面层 多晶第二材料的第二基板，以便在所述多晶层和所述第二基板之间形成接合界面; 从称为供体基板的一个基板的自由表面去除其厚度，使得仅保留薄层; 通过所述多晶材料层的非晶化在所述第一基板和所述接合界面之间产生非晶半导体材料层; 并且使非晶半导体材料层结晶，所述新结晶层具有与相邻的第一衬底相同的取向。

公开(公告)号：US20150364364A1

公开(公告)日：2015-12-17

申请号：US14377738

申请日：2013-01-28

Applicant: SOITEC

Inventor： Gweltaz Gaudin ,  Oleg Kononchuk ,  Ionut Radu

IPC: H01L21/762 ,  B32B7/04 ,  B32B9/04

CPC classification number: H01L21/76254 ,  B32B7/04 ,  B32B9/04 ,  B32B2457/14 ,  Y10T428/24802

Abstract: A method comprising the following steps: providing a support substrate and a donor substrate, forming an embrittlement region in the donor substrate so as to delimit a first portion and a second portion on either side of the embrittlement region, assembling the donor substrate on the support substrate, fracturing the donor substrate along the embrittlement. In addition, the method comprises a step consisting of forming a compressive stress layer in the donor substrate so as to delimit a so-called confinement region interposed between the compressive stress layer and the embrittlement region.

Abstract translation: 一种包括以下步骤的方法：提供支撑衬底和供体衬底，在所述供体衬底中形成脆化区域，以限定所述脆化区域的任一侧上的第一部分和第二部分，将所述施主衬底组装在所述支撑体上 底物，沿着脆化破坏施主衬底。 此外，该方法包括在施主衬底中形成压应力层以限定介于压应力层和脆化区之间的所谓约束区的步骤。

公开(公告)号：US20140225182A1

公开(公告)日：2014-08-14

申请号：US14253690

申请日：2014-04-15

Applicant: Soitec

Inventor： Mohamad A. Shaheen ,  Frederic Allibert ,  Gweltaz Gaudin ,  Fabrice Lallement ,  Didier Landru ,  Karine Landry ,  Carlos Mazure

IPC: H01L29/786

CPC classification number: H01L29/78603 ,  H01L29/32 ,  H01L29/7841 ,  H01L31/0248

Abstract: A substrate comprises a base wafer, an insulating layer over the base wafer, and a top semiconductor layer over the insulating layer on a side thereof opposite the base wafer. The insulating layer comprises a charge-confining layer confined on one or both sides with diffusion barrier layers, wherein the charge-confining layer has a density of charges in absolute value higher than 1010 charges/cm2. Alternatively, the insulating layer comprises charge-trapping islands embedded therein, wherein the charge-trapping islands have a total density of charges in absolute value higher than 1010 charges/cm2.

Abstract translation: 衬底包括基底晶片，在基底晶片上方的绝缘层，以及在与基底晶片相对的一侧上的绝缘层上的顶部半导体层。 绝缘层包括限制在具有扩散阻挡层的一侧或两侧的电荷限制层，其中电荷限制层的绝对值的电荷密度高于1010电荷/ cm 2。 或者，绝缘层包括嵌入其中的电荷捕获岛，其中电荷捕获岛具有高于1010电荷/ cm 2的绝对值的电荷的总密度。

公开(公告)号：US20130210171A1

公开(公告)日：2013-08-15

申请号：US13838031

申请日：2013-03-15

Applicant: SOITEC

Inventor： Gweltaz Gaudin

IPC: H01L21/18

CPC classification number: H01L21/185 ,  B32B37/144 ,  B32B37/18 ,  B32B38/1808 ,  B32B38/1866 ,  B32B41/00 ,  B32B2041/04 ,  B32B2307/202 ,  B32B2309/72 ,  B32B2457/14 ,  H01L21/187 ,  H01L24/75 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/75702 ,  H01L2224/75703 ,  H01L2224/75756 ,  H01L2224/75901 ,  H01L2224/80006 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/94 ,  H01L2924/3511 ,  Y10T156/10 ,  Y10T156/1089 ,  Y10T156/1092 ,  H01L2224/80

Abstract: A method for bonding a first wafer on a second wafer by molecular adhesion, where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment.

Abstract translation: 一种用于通过分子粘合将第一晶片接合在第二晶片上的方法，其中晶片在它们之间具有初始的径向不对准。 该方法包括使两个晶片接触，以便在两个晶片之间启动键合波的传播，同时在接触步骤期间将两个晶片中的至少一个施加预定的接合曲率作为初始径向失准的函数 。