公开(公告)号：US20210050297A1

公开(公告)日：2021-02-18

申请号：US16849629

申请日：2020-04-15

Applicant: Samsung Electronics Co., Ltd

Inventor： Jihwang Kim ,  Jeongmin Kang ,  Hyunkyu Kim ,  Jongbo Shim ,  Kyoungsei Choi

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package is provided including a package substrate. The package substrate includes a substrate pattern and a substrate insulation layer at least partially surrounding the substrate pattern. The package substrate has a groove. An external connection terminal is disposed below the package substrate. An embedded semiconductor device is disposed within the groove of the package substrate. The embedded semiconductor device includes a first substrate. A first active layer is disposed on the first substrate. A first chip pad is disposed on the first active layer. A buried insulation layer is disposed within the groove of the package substrate and at least partially surrounds at least a portion of a lateral surface of the embedded semiconductor device. A mounted semiconductor device is disposed on the package substrate and is connected to the package substrate and the embedded semiconductor device.

公开(公告)号：US12148729B2

公开(公告)日：2024-11-19

申请号：US17577653

申请日：2022-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Jihwang Kim ,  Jongbo Shim

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/10

Abstract: A semiconductor package structure includes a package substrate; a semiconductor chip on the package substrate and electrically connected to the package substrate; an interposer substrate above the package substrate and the semiconductor chip, wherein the interposer substrate includes a cavity recessed inward from a lower surface thereof, wherein the semiconductor chip is positioned within the cavity, at least from a plan view; and an adhesive layer positioned inside and outside the cavity, wherein the adhesive layer is formed on all of upper and side surfaces of the semiconductor chip, or on the side surfaces of the semiconductor chip.

公开(公告)号：US20240113001A1

公开(公告)日：2024-04-04

申请号：US18212939

申请日：2023-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyounglim SUK ,  Jihwang Kim ,  Suchang Lee ,  Hyeonjeong Hwang

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/64 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/642 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16227

Abstract: A semiconductor package includes: a first redistribution structure including at least one first redistribution layer and at least one first insulating layer; a first semiconductor chip electrically connected to the at least one first redistribution layer and disposed on a first surface of the first redistribution structure; a second semiconductor chip disposed on an upper surface of the first semiconductor chip; a first encapsulant disposed on a second surface of the first redistribution structure opposite the first surface of the first redistribution layer; first conductive posts electrically connected to the first semiconductor chip and penetrating the first encapsulant; and under bump metallurgy (UBM) structures disposed on a lower surface of the first encapsulant, wherein at least a portion of the UBM structures overlap at least a portion of the first conductive posts in a penetration direction of the first conductive posts and are connected to the first conductive posts.

公开(公告)号：US20240040806A1

公开(公告)日：2024-02-01

申请号：US18125928

申请日：2023-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsung Kim ,  Jihwang Kim ,  Jeongho Lee ,  Dongwook Kim ,  Wonkyoung Choi ,  Yunseok Choi

IPC: H10B80/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/36

CPC classification number: H10B80/00 ,  H01L23/5383 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/16 ,  H01L23/36 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253

Abstract: A semiconductor package includes a lower package, an upper package on the lower package, and an inter-package connector between the lower package and the upper package. The lower package includes a first redistribution structure, a first semiconductor chip mounted on a first mounting region of the first redistribution structure, a second semiconductor chip mounted on a second mounting region of the first redistribution structure, a molding layer on the first redistribution structure and in contact with a side wall of the first semiconductor chip and a side wall of the second semiconductor chip, and a conductive post passing through the molding layer and electrically connected to the first semiconductor chip through a first redistribution pattern of the first redistribution structure. The upper package is on the molding layer, vertically overlaps with the second mounting region of the first redistribution structure, and does not cover the first semiconductor chip.

公开(公告)号：US11817401B2

公开(公告)日：2023-11-14

申请号：US17510749

申请日：2021-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho Kim ,  Jihwang Kim

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor package including a semiconductor chip, a lower redistribution layer under the semiconductor chip, the lower redistribution layer including a lower insulating layer at a central region and at a portion of an edge region, and a trench at a remaining portion of the edge region, a plurality of outer connecting terminals under the lower redistribution layer, a molding layer including a first molding section and the second molding section, the first molding section being on the lower redistribution layer and surrounding a side surface of the semiconductor chip and the second molding section being in the trench and contacting a side surface of the lower insulating layer, and an upper redistribution layer on the molding layer may be provided. The side surface of the lower insulating layer and a side surface of the second molding section may be coplanar with each other.

公开(公告)号：US11710673B2

公开(公告)日：2023-07-25

申请号：US17376883

申请日：2021-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Dongwook Kim ,  Hyunki Kim ,  Jongbo Shim ,  Jihwang Kim ,  Sungkyu Park ,  Yongkwan Lee ,  Byoungwook Jang

IPC: H01L23/12 ,  H01L23/538

CPC classification number: H01L23/12 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386

Abstract: A semiconductor package including a first package substrate, a first semiconductor chip on the first package substrate, a first conductive connector on the first package substrate and laterally spaced apart from the first semiconductor chip, an interposer substrate on the first semiconductor chip and electrically connected to the first package substrate through the first conductive connector, the interposer substrate including a first portion overlapping the first semiconductor chip and a plurality of upper conductive pads in the first portion, a plurality of spacers on a lower surface of the first portion of the interposer substrate and positioned so as not to overlap the plurality of upper conductive pads in a plan view, and an insulating filler between the interposer substrate and the first package substrate may be provided.

公开(公告)号：US11581263B2

公开(公告)日：2023-02-14

申请号：US17024852

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Jungwoo Kim ,  Jihwang Kim ,  Jungsoo Byun ,  Jongbo Shim ,  Doohwan Lee ,  Kyoungsei Choi ,  Junggon Choi ,  Sungeun Pyo

IPC: H01L23/495 ,  H01L23/538 ,  H01L25/10

Abstract: A semiconductor package includes: a redistribution layer including a plurality of redistribution insulating layers, a plurality of redistribution line patterns that constitute lower wiring layers, and a plurality of redistribution vias that are connected to some of the plurality of redistribution line patterns while penetrating at least one of the plurality of redistribution insulating layers; at least one semiconductor chip arranged on the redistribution layer; an expanded layer surrounding the at least one semiconductor chip on the redistribution layer; and a cover wiring layer including at least one base insulating layer, a plurality of wiring patterns that constitute upper wiring layers, and a plurality of conductive vias that are connected to some of the plurality of wiring patterns while penetrating the at least one base insulating layer.

公开(公告)号：US20240321839A1

公开(公告)日：2024-09-26

申请号：US18530542

申请日：2023-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon Mun ,  Kyounglim Suk ,  Jihwang Kim

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A semiconductor package includes a first redistribution structure including a first redistribution insulating layer and a first redistribution pattern, a first lower semiconductor device mounted on the first redistribution structure, a molding layer surrounding the first lower semiconductor device on the first redistribution structure, a plurality of vertical connection conductors in the molding layer and electrically connected to the first redistribution pattern, a heat dissipation plate disposed on an upper surface of the first lower semiconductor device, and a plurality of upper semiconductor devices disposed on the molding layer and on the first lower semiconductor device, each of the plurality of upper semiconductor devices vertically overlapping a different respective region of the first lower semiconductor device.

公开(公告)号：US12021036B2

公开(公告)日：2024-06-25

申请号：US17986169

申请日：2022-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongbo Shim ,  Jihwang Kim ,  Choongbin Yim

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A semiconductor package comprises a package substrate, a semiconductor chip on the package substrate, and an interposer substrate on the semiconductor chip. The interposer substrate comprises a first surface facing the semiconductor chip and a trench in the first surface, the trench vertically overlapping the semiconductor chip. An insulating filler is provided between the semiconductor chip and the interposer substrate, and at least partially fills the trench of the interposer substrate.

公开(公告)号：US20240120280A1

公开(公告)日：2024-04-11

申请号：US18214341

申请日：2023-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon Mun ,  Shanghoon Seo ,  Jihwang Kim ,  Sangjin Baek ,  Hyeonjeong Hwang

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/5383 ,  H01L21/561 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/16 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L24/06 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/14511 ,  H01L2924/19106

Abstract: A semiconductor package includes a first redistribution structure, a first semiconductor device mounted on the first redistribution structure, a molding layer surrounding the first semiconductor device, a second redistribution structure disposed on the molding layer and the first semiconductor device, a plurality of vertical connection conductors vertically extending in the molding layer and electrically connecting the first redistribution pattern to the second redistribution pattern, a second semiconductor device mounted on the second redistribution structure, the second semiconductor device and the first semiconductor device vertically and partially overlapping each other, a heat dissipation pad structure contacting an upper surface of the first semiconductor device, and a heat dissipation plate disposed on the heat dissipation pad structure and spaced apart from the second semiconductor device along a first straight line extending in a horizontal direction that is parallel to the upper surface of the first semiconductor device.