公开(公告)号：US20040141140A1

公开(公告)日：2004-07-22

申请号：US10752526

申请日：2004-01-08

Applicant: Semiconductor Energy Laboratory Co., Ltd., a Japan corporation

Inventor： Hongyong Zhang ,  Shunpei Yamazaki ,  Satoshi Teramoto ,  Yoshiharu Hirakata

IPC: G02F001/1345

CPC classification number: G02F1/1339 ,  G02F1/1345 ,  G02F1/13454 ,  G02F1/136277 ,  G09G3/3648 ,  G09G2320/0252

Abstract: There is provided a configuration of an active matrix type liquid crystal display integrated with a peripheral driving circuit in which the surface area of regions excluding pixels is minimized. Further, the reliability of an apparatus having such a configuration is improved. A configuration is provided in which a sealing material 104 is provided on a peripheral driving circuit. With this configuration, layers 240 and 237 made of a resin material are provided under the sealing material 104. This makes it possible to moderate the application of a local stress to the peripheral driving circuit due to the presence of a filler 103 included in the sealing material 104. Thus, breakage of the peripheral driving circuit can be avoided.

Abstract translation: 提供了与外围驱动电路集成的有源矩阵型液晶显示器的结构，其中除了像素之外的区域的表面积最小化。 此外，具有这种配置的设备的可靠性得到改善。 提供了一种在外围驱动电路上设置密封材料104的构造。 利用这种构造，在密封材料104的下方设置有由树脂材料制成的层240和237.这使得可以通过包含在密封件中的填料103的存在来调节对外围驱动电路施加的局部应力 材料104.因此，可以避免外围驱动电路的损坏。

公开(公告)号：US20040132233A1

公开(公告)日：2004-07-08

申请号：US10739045

申请日：2003-12-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Akiharu Miyanaga ,  Toru Mitsuki ,  Hisashi Ohtani

IPC: H01L021/00

CPC classification number: H01L29/78603 ,  H01L21/02532 ,  H01L21/02672 ,  H01L21/3226 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1277 ,  H01L27/1281 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78621

Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 nullm or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.

Abstract translation: 在石英或半导体基板100上形成用于制造绝缘层104的绝缘膜103.形成在绝缘膜103的表面上的与基板100的凹部101a〜101d对应的凹部105a〜105d。 绝缘膜103被平坦化以形成下部绝缘层104.通过该平坦化处理，距离L1，L2， 。 。 下绝缘层104的凹部106a，106b，106d之间的Ln为0.3μm以上，各凹部的深度为10nm以下。 下绝缘膜104的表面的均方根表面粗糙度为0.3nm以下。 由此，在凹部106a，106b，106d中，可以避免阻止半导体薄膜的晶体生长，并且晶粒边界可以基本消失。

公开(公告)号：US20040130020A1

公开(公告)日：2004-07-08

申请号：US10740422

申请日：2003-12-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideaki Kuwabara ,  Toru Takayama ,  Yuugo Goto ,  Junya Maruyama ,  Yumiko Ohno ,  Shunpei Yamazaki

IPC: H01L029/93

CPC classification number: H01L25/50 ,  H01L21/2007 ,  H01L21/76251 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2224/45099

Abstract: A technique for manufacturing a low-cost, small volume, and highly integrated semiconductor device is provided. A characteristic of the present invention is that a semiconductor element formed by using a semiconductor thin film is transferred over a semiconductor element formed by using a semiconductor substrate by a transfer technique in order to manufacture a semiconductor device. Compared with the conventional manufacturing method, mass production of semiconductor devices with lower cost and higher throughput can be realized, and production cost per semiconductor device can be reduced.

Abstract translation: 提供了一种用于制造低成本，小体积和高度集成的半导体器件的技术。 本发明的特征在于，通过使用半导体薄膜形成的半导体元件通过转印技术通过使用半导体衬底形成的半导体元件转印以制造半导体器件。 与以往的制造方法相比，能够实现成本低，吞吐量更高的半导体装置的批量生产，能够降低半导体装置的生产成本。

公开(公告)号：US20040121516A1

公开(公告)日：2004-06-24

申请号：US10728933

申请日：2003-12-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Toru Takayama ,  Junya Maruyama ,  Yumiko Ohno ,  Koichiro Tanaka

IPC: H01L021/428

CPC classification number: H01L21/02667 ,  C30B13/24 ,  C30B29/06 ,  H01L21/02683 ,  H01L21/02686 ,  H01L21/2026 ,  H01L21/6835 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68354 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2223/54473 ,  H01L2224/1134 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/29198 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2225/06524 ,  H01L2225/06555 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/0106 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/3512

Abstract: According to the package and the method for manufacturing the package of the present invention, a chip can be formed extremely to be thin, and manufactured at lower cost and higher throughput, and the variations of a chip thickness can be reduced without back grind that causes cracks or polishing marks. In the present invention, a semiconductor film with a thickness of at most 500 nullm deposited over a substrate serving as a support medium is crystallized with a CW laser light, and a chip having a semiconductor device is formed to have a total thickness of 5 nullm, preferably at most 2 nullm by using the crystallized semiconductor film. Consequently, the chip is mounted on an interposer after separating a substrate.

Abstract translation: 根据本发明的封装和封装的制造方法，可以将芯片形成得非常薄，并以较低的成本和较高的生产量进行制造，并且可以减少芯片厚度的变化，而不会造成后面的研磨 裂纹或抛光痕迹。 在本发明中，沉积在用作支撑介质的基板上的厚度最大为500μm的半导体膜用CW激光结晶，并且具有半导体器件的芯片形成为具有5μm的总厚度 ，优选至多2μm，通过使用结晶的半导体膜。 因此，在分离衬底之后，将芯片安装在插入器上。

公开(公告)号：US20040113548A1

公开(公告)日：2004-06-17

申请号：US10720476

申请日：2003-11-25

Applicant: Semiconductor Energy Laboratory Co. Ltd., a Japan corporation

Inventor： Shunpei Yamazaki ,  Yasuyuki Arai

IPC: H05B033/00

CPC classification number: H01L51/5012 ,  H01L21/67155 ,  H01L27/3244 ,  H01L27/3246 ,  H01L27/3258 ,  H01L51/0025 ,  H01L51/5048 ,  H01L51/5088 ,  H01L51/5221 ,  H01L51/5237 ,  H01L51/5246 ,  H01L51/5253 ,  H01L51/56

Abstract: The concentration of oxygen, which causes problems such as decreases in brightness and dark spots through degradation of electrode materials, is lowered in an organic light emitting element having a layer made from an organic compound between a cathode and an anode, and in a light emitting device structured using the organic light emitting element. The average concentration of impurities contained in a layer made from an organic compound used in order to form an organic light emitting element having layers such as a hole injecting layer, a hole transporting layer, a light emitting layer, an electron transporting layer, and an electron injecting layer, is reduced to 5null1019/cm2 or less, preferably equal to or less than 1null1019/cm2, by removing the impurities with the present invention. Formation apparatuses are structured as stated in the specification in order to reduce the impurities in the organic compounds forming the organic light emitting elements.

Abstract translation: 在具有由阴极和阳极之间的有机化合物制成的层的有机发光元件和发光的有机发光元件中，通过降低电极材料而导致诸如亮度和暗斑的降低等问题的氧浓度降低 使用有机发光元件构造的器件。 为了形成具有空穴注入层，空穴传输层，发光层，电子传输层等的层的有机发光元件，使用由有机化合物制成的层中所含有的杂质的平均浓度， 电子注入层通过用本发明除去杂质而降低至5×10 19 / cm 2或更小，优选等于或小于1×10 19 / cm 2。 为了减少形成有机发光元件的有机化合物中的杂质，形成装置按说明书所述进行结构化。

公开(公告)号：US20040084699A1

公开(公告)日：2004-05-06

申请号：US10693491

申请日：2003-10-27

Applicant: Semiconductor Energy Laboratory Co., Ltd. a Japan corporation

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Yoshihiro Kusuyama

IPC: H01L029/76

CPC classification number: H01L27/1296 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L2029/7863

Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.

Abstract translation: 为了形成栅电极，层叠具有低电阻的包含Al或以Al为主要成分的材料的导电膜和用于防止Al扩散到半导体层中的具有低接触电阻的导电膜，并且栅电极由 使用能够高速进行蚀刻处理的装置。

公开(公告)号：US20040075112A1

公开(公告)日：2004-04-22

申请号：US10682440

申请日：2003-10-10

Applicant: Semiconductor Energy Laboratory Co., Ltd., a Japan corporation

Inventor： Shunpei Yamazaki ,  Mayumi Mizukami ,  Yasuyuki Arai

IPC: H01L031/109

CPC classification number: H01L51/5203 ,  H01L27/12 ,  H01L27/3244 ,  H01L27/3246 ,  H01L27/3276 ,  H01L27/3281 ,  H01L51/524 ,  H01L51/5253 ,  H01L51/5259

Abstract: Two aspects, an impurity factor and a structural factor are assumed as the deterioration causes of an organic light emitting device and means for solving the respective factors are provided. In order to prevent deterioration of the light emitting device, concentrations of moisture and oxygen, which are left in a space in which an organic light emitting element is sealed, are minimized. At the same time, an impurity including oxygen, such as moisture or oxygen which is included in an organic compound composing the organic light emitting element, is reduced. An element structure for preventing the deterioration of the organic light emitting element due to stress is used to suppress the deterioration.

公开(公告)号：US20040061438A1

公开(公告)日：2004-04-01

申请号：US10664731

申请日：2003-09-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kunitaka Yamamoto ,  Toshimitsu Konuma

IPC: H05B033/00

CPC classification number: H01L51/5253 ,  H01L23/3171 ,  H01L27/1214 ,  H01L27/1248 ,  H01L27/322 ,  H01L27/3244 ,  H01L27/3258 ,  H01L29/78621 ,  H01L51/529 ,  H01L51/56 ,  H01L2924/0002 ,  Y10S428/917 ,  H01L2924/00

Abstract: An object of the present invention is to provide an EL display device, which has a high operating performance and reliability. A third passivation film 45 is disposed under an EL element 203 which comprises a pixel electrode (anode) 46, an EL layer 47 and a cathode 48, to make a structure in which heat generated by the EL element 203 is radiated. Further, the third passivation film 45 prevents alkali metals within the EL element 203 from diffusing into the TFTs side, and prevents moisture and oxygen of the TFTs side from penetrating into the EL element 203. More preferably, heat radiating effect is given to a fourth passivation film 50 to make the EL element 203 to be enclosed by heat radiating layers.

Abstract translation: 本发明的目的是提供一种具有高操作性能和可靠性的EL显示装置。 第三钝化膜45设置在包括像素电极（阳极）46，EL层47和阴极48的EL元件203的下方，以形成其中辐射由EL元件203产生的热量的结构。 此外，第三钝化膜45防止EL元件203内的碱金属扩散到TFT侧，并且防止TFT侧的水分和氧气渗透到EL元件203中。更优选地，将散热效果提供给第四钝化膜 钝化膜50以使EL元件203被散热层包围。

公开(公告)号：US20040051142A1

公开(公告)日：2004-03-18

申请号：US10640939

申请日：2003-08-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiroki Adachi

IPC: H01L027/01

CPC classification number: H01L29/6675 ,  H01L27/124 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L2029/7863

Abstract: The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode being in contact with the first gate electrode and a gate insulating film. Further, the LDD is formed by using the first gate electrode as a mask, and source and drain regions are formed by using the second gate electrode as the mask. Then, the LDD overlapping with the second gate electrode is formed. This structure provides the thin film transistor with high reliability.

Abstract translation: 本发明涉及一种半导体器件，其包括由具有新颖的GOLD（栅极重叠LDD（轻掺杂漏极））结构的薄膜晶体管构成的电路。 薄膜晶体管包括与第一栅极电极和栅极绝缘膜接触的第一栅电极和第二电极。 此外，通过使用第一栅电极作为掩模来形成LDD，并且通过使用第二栅电极作为掩模形成源区和漏区。 然后，形成与第二栅电极重叠的LDD。 该结构提供了具有高可靠性的薄膜晶体管。

公开(公告)号：US20040051100A1

公开(公告)日：2004-03-18

申请号：US10642803

申请日：2003-08-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yoshiharu Hirakata ,  Satoshi Murakami

IPC: G02F001/136 ,  H01L031/036

CPC classification number: G02F1/1368 ,  G02F1/13394 ,  G02F1/134363 ,  G02F1/13454 ,  G02F1/136213 ,  G02F1/136227 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78675

Abstract: A method of forming a storage capacitor in an IPS liquid crystal display device is proposed, and a technique of forming a pixel region having a high aperture ratio is provided. An anodic oxidation process at an applied voltage/voltage supply time ratio of 11 V/min is performed for insulating films used in each circuit of an electro-optical device, typically an IPS method LCD, in particular for the surface of a common electrode formed on a resin film. The amount of formation of the extra anodic oxide film can be reduced by covering with an anodic oxide film, and a liquid crystal display device with high reliability and having an electrode with superior adhesion can be manufactured.

Abstract translation: 提出了一种在IPS液晶显示装置中形成存储电容器的方法，并且提供了形成具有高开口率的像素区域的技术。 对于电光装置的每个电路中使用的绝缘膜（通常为IPS方法LCD），特别是形成的公共电极的表面，对施加的电压/电压供给时间比为11V / min进行阳极氧化处理 在树脂膜上。 可以通过用阳极氧化膜覆盖来减少额外的阳极氧化膜的形成量，并且可以制造具有高可靠性和具有优异粘附性的电极的液晶显示装置。