-
公开(公告)号：US20160020190A1
公开(公告)日：2016-01-21
申请号：US14744464
申请日：2015-06-19
Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Inventor： Wen-Kuang Wu , Tsung-Te Yuan , Chun-Hung Lu
CPC classification number: H01L24/97 , H01L21/481 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/147 , H01L23/49816 , H01L23/49827 , H01L23/5226 , H01L24/14 , H01L24/81 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81002 , H01L2924/00
Abstract: A method for fabricating an interposer is provided, which includes the steps of: providing a substrate body having a chip mounting side and an opposite external connection side and a plurality of conductive through holes communicating the chip mounting side and the external connection side, wherein the chip mounting side of the substrate body is covered with a protection layer; performing a singulation process on the external connection side of the substrate body; bonding the substrate body to a carrier via the external connection side thereof; removing the protection layer; and removing the carrier to form a plurality of interposers, thereby simplifying the fabrication process and improving the product yield.
Abstract translation: 提供了一种制造插入件的方法，其包括以下步骤：提供具有芯片安装侧和相对的外部连接侧的基板主体和连接芯片安装侧和外部连接侧的多个导电通孔，其中， 衬底主体的芯片安装侧被保护层覆盖; 在所述基板主体的外部连接侧进行切割处理; 通过其外部连接侧将衬底本体连接到载体上; 去除保护层; 并移除载体以形成多个插入物，从而简化制造工艺并提高产品产率。
-
公开(公告)号：US20150035163A1
公开(公告)日：2015-02-05
申请号：US14012402
申请日：2013-08-28
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Guang-Hwa Ma , Shih-Kuang Chiu , Shih-Ching Chen , Chun-Chi Ke , Chang-Lun Lu , Chun-Hung Lu , Hsien-Wen Chen , Chun-Tang Lin , Yi-Che Lai , Chi-Hsin Chiu , Wen-Tsung Tseng , Tsung-Te Yuan , Lu-Yi Chen , Mao-Hua Yeh
IPC: H01L23/538 , H01L23/00
CPC classification number: H01L24/96 , H01L21/568 , H01L21/6835 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/82 , H01L2221/68372 , H01L2221/68377 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/24137 , H01L2224/82005 , H01L2224/82007 , H01L2924/12042 , H01L2924/18162 , H01L2924/351 , H01L2924/3511 , H01L2924/00
Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing a semiconductor element in a groove of a carrier; forming a dielectric layer on the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second of the carrier on a sidewall of the groove intact for the second portion to function as a supporting part. The present invention does not require formation of a silicon interposer, therefore the overall cost of the final product is much reduced.
Abstract translation: 本发明提供一种半导体封装及其制造方法，包括：将半导体元件放置在载体的凹槽中; 在所述半导体元件上形成介电层; 在所述电介质层上形成电连接到所述半导体元件的电路层; 以及在所述凹槽下方移除所述载体的第一部分以将所述载体的第二载体保持在所述凹槽的侧壁上，以使所述第二部分用作支撑部分。 本发明不需要形成硅插入件，因此最终产品的总成本大大降低。
-
公开(公告)号：US10679914B2
公开(公告)日：2020-06-09
申请号：US15635446
申请日：2017-06-28
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chieh-Lung Lai , Cheng-Yi Chen , Chun-Hung Lu , Mao-Hua Yeh
Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.
-
公开(公告)号：US20180254232A1
公开(公告)日：2018-09-06
申请号：US15635446
申请日：2017-06-28
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chieh-Lung Lai , Cheng-Yi Chen , Chun-Hung Lu , Mao-Hua Yeh
Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.
-
公开(公告)号：US20180068959A1
公开(公告)日：2018-03-08
申请号：US15698136
申请日：2017-09-07
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Hui-Chuan Lu , Chun-Hung Lu , Po-Yi Wu
IPC: H01L23/00 , H01L23/498 , H01L23/16 , H01L23/31 , H01L23/14 , H01L21/48 , H01L23/538
CPC classification number: H01L23/562 , H01L21/4857 , H01L21/7684 , H01L23/147 , H01L23/16 , H01L23/3128 , H01L23/49822 , H01L23/49827 , H01L23/49866 , H01L23/5383 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00 , H01L2924/00012 , H01L2924/15311 , H01L2924/181
Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.
-
Patent Agency Ranking
公开(公告)号：US20160260644A1
公开(公告)日：2016-09-08
申请号：US14998324
申请日：2015-12-24
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Lung-Shan Chuang , Ching-Wen Chiang , Tzung-Yen Wu , Chun-Hung Lu
IPC: H01L23/053 , H01L23/31 , H01L21/78 , H01L21/683 , H01L21/48 , H01L21/56 , H01L23/06 , H01L23/498
CPC classification number: H01L23/053 , H01L21/4803 , H01L21/486 , H01L21/6835 , H01L21/78 , H01L23/147 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L24/97 , H01L2224/16227 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81005 , H01L2224/83005 , H01L2224/97 , H01L2924/15311 , H01L2924/16152 , H01L2924/16153 , H01L2924/16251 , H01L2924/167 , H01L2224/83 , H01L2224/81
Abstract: An electronic package is provided, including a circuit portion, an electronic element disposed on the circuit portion and a lid member disposed on the circuit portion to cover the electronic element. A separation portion is formed between the lid member and the electronic element. The lid member facilitates to prevent warping of the overall package structure. The invention further provides a method for fabricating the electronic package.
Abstract translation: 提供一种电子封装，包括电路部分，设置在电路部分上的电子元件和设置在电路部分上以覆盖电子元件的盖子部件。 在盖构件和电子元件之间形成分离部。 盖构件有助于防止整个包装结构的翘曲。 本发明还提供一种制造电子封装的方法。
-
公开(公告)号：US09076796B2
公开(公告)日：2015-07-07
申请号：US13894687
申请日：2013-05-15
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chun-Hung Lin , Chun-Hung Lu , Guang-Hwa Ma , Hsiao-Chun Huang , Kuang-Hsin Chen
IPC: H01L23/532 , H01L21/768 , H01L23/498
CPC classification number: H01L23/53295 , H01L21/76802 , H01L21/76808 , H01L23/49894 , H01L23/53238 , H01L23/5329 , H01L2221/1031 , H01L2924/0002 , H01L2924/00
Abstract: An interconnection structure for a package is disclosed. The interconnection structure includes a substrate body having a conductive portion formed on a surface thereof; a first photosensitive dielectric layer formed on the surface of the substrate body and having a via for exposing the conductive potion; a conductive via formed in the via; a second photosensitive dielectric layer formed on the first photosensitive dielectric layer and having a opening for exposing the conductive via and a portion of the first photosensitive dielectric layer; and a conductive trace layer formed in the opening of the second photosensitive dielectric layer so as to be electrically connected to the conductive portion through the conductive via, thereby simplifying the fabrication process and reducing the fabrication cost and time.
Abstract translation: 公开了一种用于封装的互连结构。 互连结构包括在其表面上形成有导电部分的基板主体; 形成在所述基板主体的表面上并且具有用于使所述导电部暴露的通孔的第一光敏介电层; 在通孔中形成的导电通孔; 形成在所述第一光敏介电层上并具有用于使所述导电通孔和所述第一光敏介电层的一部分暴露的开口的第二光敏介电层; 以及形成在第二感光介电层的开口中的导电迹线层，以便通过导电通孔电连接到导电部分，从而简化制造工艺并降低制造成本和时间。
-
公开(公告)号：US20140117538A1
公开(公告)日：2014-05-01
申请号：US13949557
申请日：2013-07-24
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Kuang-Hsin Chen , Chun-Hung Lu
IPC: H01L23/498 , H01L21/50
CPC classification number: H01L23/49827 , H01L21/486 , H01L23/3128 , H01L23/49816 , H01L2224/16225 , H01L2224/81192 , H01L2924/15174 , H01L2924/15311 , H01L2924/19105
Abstract: A fabrication method of a package structure is provided, which includes the steps of: providing an interposer having a plurality of recess holes; forming a conductive bump in a lower portion of each of the recess holes; forming a conductive through hole on the conductive bump in each of the recess holes; removing a portion of the interposer so as for the conductive bumps to protrude from the interposer; and mounting at least a first external element on the conductive bumps, thereby simplifying the fabrication process, shortening the process time and reducing the material cost.
Abstract translation: 提供一种封装结构的制造方法，其包括以下步骤：提供具有多个凹陷孔的插入件; 在每个凹槽的下部形成导电凸块; 在每个凹孔中的导电凸块上形成导电通孔; 去除所述插入件的一部分，以使所述导电凸起从所述插入件突出; 并且至少将第一外部元件安装在导电凸块上，从而简化制造工艺，缩短处理时间并降低材料成本。
-
公开(公告)号：US11081415B2
公开(公告)日：2021-08-03
申请号：US16862024
申请日：2020-04-29
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chieh-Lung Lai , Cheng-Yi Chen , Chun-Hung Lu , Mao-Hua Yeh
Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.
-
公开(公告)号：US20200370184A1
公开(公告)日：2020-11-26
申请号：US16991999
申请日：2020-08-12
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Po-Yi Wu , Chun-Hung Lu
IPC: C23F1/00 , H01L23/498 , H01L21/48 , H01L23/14
Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.
-
-
-
-
-
-
-
-
-
Search Results
32
records
(took 0.017 seconds)
