公开(公告)号：US20200075779A1

公开(公告)日：2020-03-05

申请号：US16661758

申请日：2019-10-23

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Luigi Colombo

IPC: H01L29/786 ,  H01L29/778 ,  H01L29/16 ,  H01L21/02 ,  H01L29/66 ,  H01L29/45 ,  H01L29/49 ,  H01L29/267 ,  H01L29/20

Abstract: A microelectronic device includes a gated graphene component. The gated graphene component has a graphitic layer containing one or more layers of graphene. The graphitic layer has a channel region, a first contact region adjacent to the channel region and a second contact region adjacent to the channel region. A patterned hexagonal boron nitride (hBN) layer is disposed on the graphitic layer above the channel region. A gate is located over the patterned hBN layer above the channel region. A first connection is disposed on the graphitic layer in the first contact region, and a second connection is disposed on the graphitic layer in the second contact region. The patterned hBN layer does not extend completely under the first connection or under the second connection. A method of forming the gated graphene component in the microelectronic device is disclosed.

公开(公告)号：US20180151470A1

公开(公告)日：2018-05-31

申请号：US15361394

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L23/522 ,  H01L23/373 ,  H01L23/00 ,  H01L21/768 ,  H01L21/48

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region has a plurality of interconnect levels. The integrated circuit includes a thermal routing structure in the interconnect region. The thermal routing structure extends over a portion, but not all, of the integrated circuit in the interconnect region. The thermal routing structure includes a cohered nanoparticle film in which adjacent nanoparticles cohere to each other. The thermal routing structure has a thermal conductivity higher than dielectric material touching the thermal routing structure. The cohered nanoparticle film is formed by a method which includes an additive process.

公开(公告)号：US20180151467A1

公开(公告)日：2018-05-31

申请号：US15361403

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L23/373 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/02

CPC classification number: H01L21/02354 ,  H01L21/02288 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/34 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3737 ,  H01L23/4334 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/32245 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A packaged electronic device includes an integrated circuit and an electrically non-conductive encapsulation material in contact with the integrated circuit. A thermal conduit extends from an exterior of the package, through the encapsulation material, to the integrated circuit. The thermal conduit has a thermal conductivity higher than the encapsulation material contacting the thermal conduit. The thermal conduit includes a cohered nanoparticle film. The cohered nanoparticle film is formed by a method which includes an additive process.

公开(公告)号：US09793214B1

公开(公告)日：2017-10-17

申请号：US15438174

申请日：2017-02-21

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L23/522 ,  H01L23/66

CPC classification number: H01L23/53276 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53271 ,  H01L23/66 ,  H01L2223/6616

Abstract: An integrated circuit includes an interconnect which includes a metal layer, a layer of graphene on at least one of the top surface of the interconnect or the bottom surface of the interconnect, and a layer of hexagonal boron nitride (hBN) on the layer of graphene, opposite from the metal layer. Dielectric material of the integrated circuit contacts the layer of hBN. The layer of graphene has one or more atomic layers of graphene. The layer of hBN is one to three atomic layers thick. The interconnect may have a lower graphene layer on the bottom surface of the metal layer with a lower hBN layer, and an upper graphene layer on the top surface of the metal layer, with an upper hBN layer.

公开(公告)号：US09496198B2

公开(公告)日：2016-11-15

申请号：US14499222

申请日：2014-09-28

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Marie Denison ,  Luigi Colombo ,  Hiep Nguyen ,  Darvin Edwards

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L23/373 ,  H01L21/4871 ,  H01L21/4889 ,  H01L23/367 ,  H01L23/3675 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L2224/03416 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05073 ,  H01L2224/05078 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05193 ,  H01L2224/05558 ,  H01L2224/05578 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05687 ,  H01L2224/05693 ,  H01L2224/08165 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83447 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/04941 ,  H01L2924/014 ,  H01L2924/01006 ,  H01L2924/0503 ,  H01L2924/01005 ,  H01L2924/01074 ,  H01L2224/45099 ,  H01L2224/03

Abstract: A microelectronic device includes semiconductor device with a component at a front surface of the semiconductor device and a backside heat spreader layer on a back surface of the semiconductor device. The backside heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.

Abstract translation: 微电子器件包括在半导体器件的前表面处具有部件的半导体器件和在半导体器件的背面上的背面散热器层。 背面散热器层为100纳米至3微米厚，面内热导率至少为150瓦特/米-2°K，电阻率小于100微欧姆厘米。

公开(公告)号：US20250066526A1

公开(公告)日：2025-02-27

申请号：US18942875

申请日：2024-11-11

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo

IPC: C08F292/00 ,  C08F8/42 ,  C08J5/00 ,  C08K3/04 ,  C08K3/08 ,  C08K7/00 ,  C08L25/06 ,  C08L33/12 ,  G03F1/78

Abstract: A method of forming a composite material includes photo-initiating a polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice. Unpolymerized monomer is removed from the polymer microlattice. The polymer microlattice is coated with a metal. The metal-coated polymer microlattice is dispersed in a polymer matrix.

公开(公告)号：US20230378023A1

公开(公告)日：2023-11-23

申请号：US17952111

申请日：2022-09-23

Applicant: Texas Instruments Incorporated

Inventor： Vinod Rai ,  Archana Venugopal ,  Blake Travis

IPC: H01L23/42 ,  H01L23/522 ,  H01L23/485 ,  H01L21/66

CPC classification number: H01L23/42 ,  H01L23/5228 ,  H01L23/485 ,  H01L22/12

Abstract: An electronic device includes a package structure, conductive leads partially exposed outside the package structure, and a semiconductor die having a semiconductor layer and a multilevel metallization structure, where the semiconductor die is enclosed by the package structure and the multilevel metallization structure includes a heater resistor, a sense resistor, and conductive metal features electrically coupled to respective terminals of the heater resistor and the sense resistor, with the conductive metal features electrically coupled to respective ones of the conductive leads.

公开(公告)号：US20230307312A1

公开(公告)日：2023-09-28

申请号：US18143446

申请日：2023-05-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L23/373 ,  H01L21/48

CPC classification number: H01L23/3677 ,  H01L23/3733 ,  H01L21/4882 ,  H01L23/3731 ,  H01L23/3736

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a thermal via in the interconnect region. The thermal via extends vertically in at least one of the interconnect levels in the interconnect region. The thermal via includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal via has a thermal conductivity higher than dielectric material touching the thermal via. The cohered nanoparticle film is formed by a method which includes an additive process.

公开(公告)号：US20230200238A1

公开(公告)日：2023-06-22

申请号：US17836731

申请日：2022-06-09

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Jingjing Chen

IPC: H01L35/30 ,  H01L35/24 ,  H01L35/32

CPC classification number: H01L35/30 ,  H01L35/24 ,  H01L35/32

Abstract: A microelectronic device including a substrate having a semiconductor material containing an embedded thermoelectric cooler with thermally anisotropic mesas between the cold terminal and the hot terminal of the embedded thermoelectric cooler adjacent to a heat source; the adjacent embedded thermoelectric cooler providing a temperature reduction for the heat source resulting in increased safe operating area (SOA) for the microelectronic device. The thermally anisotropic mesas are formed in parallel with deep trenches used as isolation in the microelectronic device.

公开(公告)号：US11676880B2

公开(公告)日：2023-06-13

申请号：US15361399

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/367 ,  H01L23/373 ,  H01L21/48

CPC classification number: H01L23/3677 ,  H01L21/4882 ,  H01L23/3731 ,  H01L23/3733 ,  H01L23/3736

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a thermal via in the interconnect region. The thermal via extends vertically in at least one of the interconnect levels in the interconnect region. The thermal via includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal via has a thermal conductivity higher than dielectric material touching the thermal via. The cohered nanoparticle film is formed by a method which includes an additive process.