公开(公告)号：US20160300722A1

公开(公告)日：2016-10-13

申请号：US15180481

申请日：2016-06-13

Applicant: Texas Instruments Incorporated

Inventor： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/49 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

Abstract translation: 可以减少在制造栅极电介质结构中使用的工艺之间发生的栅极介电层的氧化物生长。 氧化物生长的减少可以通过将栅极电介质层保持在有效的方式来实现，以在制造栅极电介质结构中的至少两个顺序的工艺步骤之间减轻栅极电介质层的氧化物生长。 维持栅极电介质层在有效减少氧化物生长的环境中也改善了注入栅电介质的氮的均匀性。

公开(公告)号：US09368355B2

公开(公告)日：2016-06-14

申请号：US14858227

申请日：2015-09-18

Applicant: Texas Instruments Incorporated

Inventor： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC: H01L21/28 ,  H01L21/316 ,  H01L21/318 ,  H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L21/67 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/677 ,  H01L21/324 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

公开(公告)号：US20190259827A1

公开(公告)日：2019-08-22

申请号：US15902829

申请日：2018-02-22

Applicant: Texas Instruments Incorporated

Inventor： Poornika Fernandes ,  Luigi Colombo ,  Haowen Bu

IPC: H01L49/02 ,  C23C16/455 ,  H01G4/018 ,  H01L21/677

Abstract: In a described example, a method for forming a capacitor includes: forming a capacitor first plate over a non-conductive substrate; flowing ammonia and nitrogen gas into a plasma enhanced chemical vapor deposition (PECVD) chamber containing the non-conductive substrate; stabilizing a pressure and a temperature in the PECVD chamber; turning on radio frequency high frequency (RF-HF) power to the PECVD chamber; pretreating the capacitor first plate for at least 60 seconds; depositing a capacitor dielectric on the capacitor first plate; and depositing a capacitor second plate on the capacitor dielectric.

公开(公告)号：US20190259826A1

公开(公告)日：2019-08-22

申请号：US15902764

申请日：2018-02-22

Applicant: Texas Instruments Incorporated

Inventor： Poornika Fernandes ,  Luigi Colombo ,  Haowen Bu

IPC: H01L49/02 ,  H01L21/02 ,  H01L29/06 ,  H01G4/08 ,  H01L27/06

Abstract: In a described example, an integrated circuit includes a capacitor first plate; a dielectric stack over the capacitor first plate comprising silicon nitride and silicon dioxide with a capacitance quadratic voltage coefficient less than 0.5 ppm/V2; and a capacitor second plate over the dielectric stack.

公开(公告)号：US20180130662A1

公开(公告)日：2018-05-10

申请号：US15865758

申请日：2018-01-09

Applicant: Texas Instruments Incorporated

Inventor： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC: H01L21/28 ,  C23C16/455 ,  C23C16/458 ,  H01J37/32 ,  H01L29/51 ,  H01L21/02

CPC classification number: H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

公开(公告)号：US20170133228A1

公开(公告)日：2017-05-11

申请号：US15404561

申请日：2017-01-12

Applicant: Texas Instruments Incorporated

Inventor： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC: H01L21/28 ,  H01L21/67

CPC classification number: H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

公开(公告)号：US09305998B2

公开(公告)日：2016-04-05

申请号：US14175838

申请日：2014-02-07

Applicant: Texas Instruments Incorporated

Inventor： Bhaskar Srinivasan ,  Eric H. Warninghoff ,  Alan Merriam ,  Haowen Bu ,  Brian E. Goodlin ,  Manoj K. Jain

IPC: H01L21/00 ,  H01L49/02 ,  H01L21/02 ,  C23C16/02 ,  C23C16/40 ,  H01L27/115

CPC classification number: H01L28/75 ,  C23C16/0281 ,  C23C16/409 ,  H01L21/02197 ,  H01L21/02271 ,  H01L21/02304 ,  H01L27/11502 ,  H01L28/55

Abstract: Deposition of lead-zirconium-titanate (PZT) ferroelectric material over iridium metal, in the formation of a ferroelectric capacitor in an integrated circuit. The capacitor is formed by the deposition of a lower conductive plate layer having iridium metal as a top layer. The surface of the iridium metal is thermally oxidized, prior to or during the deposition of the PZT material. The resulting iridium oxide at the surface of the iridium metal is very thin, on the order of a few nanometers, which allows the deposited PZT to nucleate according to the crystalline structure of the iridium metal rather than that of iridium oxide. The iridium oxide is also of intermediate stoichiometry (IrO2-x), and reacts with the PZT material being deposited.

Abstract translation: 在铱金属上沉积钛酸锆（PZT）铁电材料，在集成电路中形成铁电电容器。 通过沉积具有铱金属的下导电板层作为顶层形成电容器。 铱金属的表面在PZT材料沉积之前或期间被热氧化。 在铱金属表面的所得铱氧化物非常薄，几毫米数量级，这允许沉积的PZT根据铱金属的晶体结构而不是氧化铱的晶体结构成核。 氧化铱也具有中等化学计量（IrO2-x），并与沉积的PZT材料发生反应。

公开(公告)号：US20140227805A1

公开(公告)日：2014-08-14

申请号：US14175838

申请日：2014-02-07

Applicant: Texas Instruments Incorporated

Inventor： Bhaskar Srinivasan ,  Eric H. Warninghoff ,  Alan Merriam ,  Haowen Bu ,  Brian E. Goodlin ,  Manoj K. Jain

IPC: H01L49/02

CPC classification number: H01L28/75 ,  C23C16/0281 ,  C23C16/409 ,  H01L21/02197 ,  H01L21/02271 ,  H01L21/02304 ,  H01L27/11502 ,  H01L28/55

Abstract: Deposition of lead-zirconium-titanate (PZT) ferroelectric material over iridium metal, in the formation of a ferroelectric capacitor in an integrated circuit. The capacitor is formed by the deposition of a lower conductive plate layer having iridium metal as a top layer. The surface of the iridium metal is thermally oxidized, prior to or during the deposition of the PZT material. The resulting iridium oxide at the surface of the iridium metal is very thin, on the order of a few nanometers, which allows the deposited PZT to nucleate according to the crystalline structure of the iridium metal rather than that of iridium oxide. The iridium oxide is also of intermediate stoichiometry (IrO2-x), and reacts with the PZT material being deposited.

Abstract translation: 在铱金属上沉积钛酸锆（PZT）铁电材料，在集成电路中形成铁电电容器。 通过沉积具有铱金属的下导电板层作为顶层形成电容器。 铱金属的表面在PZT材料沉积之前或期间被热氧化。 在铱金属表面的所得铱氧化物非常薄，几毫米数量级，这允许沉积的PZT根据铱金属的晶体结构而不是氧化铱的晶体结构成核。 氧化铱也具有中等化学计量（IrO2-x），并与沉积的PZT材料发生反应。

公开(公告)号：US20240349510A1

公开(公告)日：2024-10-17

申请号：US18479006

申请日：2023-09-30

Applicant: Texas Instruments Incorporated

Inventor： Haowen Bu ,  Roger C. McDermott ,  Matthew Richards

IPC: H10B53/30

CPC classification number: H10B53/30 ,  H01L28/40

Abstract: A method forms an integrated circuit, by forming a first conductive member affixed relative to a semiconductor substrate and a second conductive member affixed relative to the semiconductor substrate. The method also forms a ferroelectric member between the first and second conductive members. The ferroelectric member has a first portion including a first atomic ratio of lead (Pb) relative to other materials in the first portion and a second portion including a second atomic ratio of lead relative to other materials in the second portion, the second atomic ratio differing from the first atomic ratio.

公开(公告)号：US11569342B2

公开(公告)日：2023-01-31

申请号：US16820549

申请日：2020-03-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika Fernandes ,  Luigi Colombo ,  Haowen Bu

IPC: H01L49/02 ,  C23C16/455 ,  H01L21/677 ,  H01G4/018 ,  H03M1/12

Abstract: In a described example, a method for forming a capacitor includes: forming a capacitor first plate over a non-conductive substrate; flowing ammonia and nitrogen gas into a plasma enhanced chemical vapor deposition (PECVD) chamber containing the non-conductive substrate; stabilizing a pressure and a temperature in the PECVD chamber; turning on radio frequency high frequency (RF-HF) power to the PECVD chamber; pretreating the capacitor first plate for at least 60 seconds; depositing a capacitor dielectric on the capacitor first plate; and depositing a capacitor second plate on the capacitor dielectric.