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    Power integrated circuit including series-connected source substrate and drain substrate power mosfets
    18.
    发明授权
    Power integrated circuit including series-connected source substrate and drain substrate power mosfets 有权
    功率集成电路，包括串联源极衬底和漏极衬底电源MOSFET

    公开(公告)号：US09076671B2

    公开(公告)日：2015-07-07

    申请号：US14559390

    申请日：2014-12-03

    Applicant: Texas Instruments Incorporated

    Inventor： Christopher Boguslaw Kocon ,  Marie Denison ,  Taylor Efland

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/088 ,  H01L29/78

    CPC classification number: H01L27/088 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/7802 ,  H01L29/7803 ,  H01L29/7809 ,  H01L29/7816 ,  H01L29/7835

    Abstract: A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region parallel to channel current flow. The RESURF trenches have dielectric liners and electrically conductive RESURF elements on the liners. Source contact metal is disposed over the body region and source regions. A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer, and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region perpendicular to channel current flow. Source contact metal is disposed in a source contact trench and extended over the drain drift region to provide a field plate.

    Abstract translation: 一种半导体器件，其包含在下漏极层上方具有漏极漂移区域的高电压MOS晶体管和横向设置在衬底顶表面处的沟道区域。 RESURF沟槽穿过漏极漂移区域和与通道电流流动平行的体区域。 RESURF沟槽在衬垫上具有电介质衬垫和导电RESURF元件。 源接触金属设置在身体区域和源区域上。 一种半导体器件，其包含在下漏极层上具有漏极漂移区域的高电压MOS晶体管，以及横向设置在衬底顶表面处的沟道区域。 RESURF沟槽穿过垂直于沟道电流的漏极漂移区域和体区。 源极接触金属设置在源极接触沟槽中并在漏极漂移区域上延伸以提供场板。

    LATERAL SUPERJUNCTION EXTENDED DRAIN MOS TRANSISTOR
    19.
    发明申请
    LATERAL SUPERJUNCTION EXTENDED DRAIN MOS TRANSISTOR 有权
    横向超级扩展漏磁MOS晶体管

    公开(公告)号：US20140061789A1

    公开(公告)日：2014-03-06

    申请号：US14073472

    申请日：2013-11-06

    Applicant: Texas Instruments Incorporated

    Inventor： Marie Denison ,  Sameer Pendharkar

    IPC: H01L29/78 ,  H01L29/08

    CPC classification number: H01L29/7816 ,  H01L21/76224 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0882 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

    Abstract: An integrated circuit containing an extended drain MOS transistor with deep semiconductor (SC) RESURF trenches in the drift region, in which each deep SC RESURF trench has a semiconductor RESURF layer at a sidewall of the trench contacting the drift region. The semiconductor RESURF layer has an opposite conductivity type from the drift region. The deep SC RESURF trenches have depth:width ratios of at least 5:1, and do not extend through a bottom surface of the drift region. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching undersized trenches and counterdoping the sidewall region to form the semiconductor RESURF layer. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching trenches and growing an epitaxial layer on the sidewall region to form the semiconductor RESURF layer.

    Abstract translation: 一种集成电路，其包含在漂移区域中具有深半导体（SC）RESURF沟槽的扩展漏极MOS晶体管，其中每个深的SC RESURF沟槽在与漂移区接触的沟槽的侧壁处具有半导体RESURF层。 半导体RESURF层具有与漂移区相反的导电类型。 深的SC RESURF沟槽具有至少5：1的深度：宽度比，并且不延伸穿过漂移区域的底部表面。 通过蚀刻尺寸不足的沟槽和反向掺杂侧壁区以形成半导体RESURF层，在漂移区中形成具有深SC RESURF沟槽的集成电路的工艺。 通过蚀刻沟槽并在侧壁区域上生长外延层以形成半导体RESURF层，在漂移区中形成具有深SC RESURF沟槽的集成电路的工艺。

    Integrated Lateral High Voltage Mosfet
    20.
    发明申请
    Integrated Lateral High Voltage Mosfet 有权
    集成侧向高电压Mosfet

    公开(公告)号：US20130277739A1

    公开(公告)日：2013-10-24

    申请号：US13922381

    申请日：2013-06-20

    Applicant: Texas Instruments Incorporated

    Inventor： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower

    IPC: H01L29/78

    CPC classification number: H01L29/7816 ,  H01L21/265 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

    Abstract: An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.

    Abstract translation: 一种包含双漂移层延伸漏极MOS晶体管的集成电路，其上部漂移层沿着两个漂移层的公共长度的至少75％与下部漂移层接触。 下漂移层中的平均掺杂密度在上漂移层中的平均掺杂密度的2至10倍。 一种形成集成电路的过程，该集成电路包含在体区内具有较低漂移延伸的双漂移层延伸漏极MOS晶体管，以及使用外延工艺电隔离体区的隔离链路。 一种形成集成电路的过程，该集成电路包含在主体区域具有较低漂移延伸的双漂移层延伸漏极MOS晶体管和在整体式衬底上电隔离体区的隔离链路。

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