公开(公告)号：US10276525B2

公开(公告)日：2019-04-30

申请号：US15452674

申请日：2017-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wen Hsiao ,  Chen-Shien Chen ,  Kuo-Ching Hsu ,  Mirng-Ji Lii

IPC: H01L23/00

Abstract: A package structure is provided comprising a die, a redistribution layer, at least one integrated passive device (IPD), a plurality of solder balls and a molding compound. The die comprises a substrate and a plurality of conductive pads. The redistribution layer is disposed on the die, wherein the redistribution layer comprises first connection structures and second connection structures. The IPD is disposed on the redistribution layer, wherein the IPD is connected to the first connection structures of the redistribution layer. The plurality of solder balls is disposed on the redistribution layer, wherein the solder balls are disposed and connected to the second connection structures of the redistribution layer. The molding compound is disposed on the redistribution layer, and partially encapsulating the IPD and the plurality of solder balls, wherein top portions of the solder balls and a top surface of the IPD are exposed from the molding compound.

公开(公告)号：US09917035B2

公开(公告)日：2018-03-13

申请号：US13658895

申请日：2012-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jen Tseng ,  Yen-Liang Lin ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Mirng-Ji Lii

IPC: H01L23/488 ,  H01L23/00

CPC classification number: H01L23/488 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13565 ,  H01L2224/13686 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/81815 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/053 ,  H01L2924/206 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

Abstract: A bump-on-trace interconnection structure utilizing a lower volume solder joint for joining a conductive metal pillar and a metal line trace includes a conductive metal pillar having a bonding surface having a width WP and a metal line trace, provided on a package substrate, having a top surface with a width WT, where WP is greater than WT. The solder joint is bonded to the bonding surface by wetting across the width WP and bonded predominantly only to the top surface of the metal line trace by wetting predominantly only to the top surface across the width WT.

公开(公告)号：US20240379584A1

公开(公告)日：2024-11-14

申请号：US18780104

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Tseng ,  Yu-Feng Chen ,  Cheng Jen Lin ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Kuo-Ching Hsu ,  Hong-Seng Shue ,  Ming-Hong Cha ,  Chao-Yi Wang ,  Mirng-Ji Lii

IPC: H01L23/58 ,  H01L21/02 ,  H01L21/48 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.

公开(公告)号：US20240363457A1

公开(公告)日：2024-10-31

申请号：US18767481

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Hung Chen ,  Hong-Seng Shue ,  Po-Hao Tsai ,  Mirng-Ji Lii

IPC: H01L23/10 ,  H01L21/50 ,  H01L21/762 ,  H01L23/522

CPC classification number: H01L23/10 ,  H01L21/50 ,  H01L21/76297 ,  H01L23/5226

Abstract: A method includes forming a plurality of dielectric layers, forming a lower portion of a seal ring including a plurality of metal layers, each extending into one of the plurality of dielectric layers, depositing a first passivation layer over the plurality of dielectric layers, forming an opening in the first passivation layer, forming a via ring in the opening and physically contacting the lower portion of the seal ring, and forming a metal ring over the first passivation layer and joined to the via ring. The via ring and the metal ring form an upper portion of the seal ring. The metal ring includes an edge portion having a zigzag pattern. The method further includes forming a second passivation layer on the metal ring, and performing a singulation process to form a device die, with the seal ring being proximate edges of the device die.

公开(公告)号：US12087648B2

公开(公告)日：2024-09-10

申请号：US17659048

申请日：2022-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Hung Chen ,  Hong-Seng Shue ,  Po-Hao Tsai ,  Mirng-Ji Lii

IPC: H01L23/10 ,  H01L21/50 ,  H01L21/762 ,  H01L23/522

CPC classification number: H01L23/10 ,  H01L21/50 ,  H01L21/76297 ,  H01L23/5226

Abstract: A method includes forming a plurality of dielectric layers, forming a lower portion of a seal ring including a plurality of metal layers, each extending into one of the plurality of dielectric layers, depositing a first passivation layer over the plurality of dielectric layers, forming an opening in the first passivation layer, forming a via ring in the opening and physically contacting the lower portion of the seal ring, and forming a metal ring over the first passivation layer and joined to the via ring. The via ring and the metal ring form an upper portion of the seal ring. The metal ring includes an edge portion having a zigzag pattern. The method further includes forming a second passivation layer on the metal ring, and performing a singulation process to form a device die, with the seal ring being proximate edges of the device die.

公开(公告)号：US20240096647A1

公开(公告)日：2024-03-21

申请号：US18521284

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mirng-Ji Lii ,  Chen-Shien Chen ,  Lung-Kai Mao ,  Ming-Da Cheng ,  Wen-Hsiung Lu

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L21/4857 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5383 ,  H01L24/80 ,  H01L2224/80345 ,  H01L2224/80355

Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.

公开(公告)号：US20230061716A1

公开(公告)日：2023-03-02

申请号：US17707481

申请日：2022-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Kun Lai ,  Yi-Wen Wu ,  Kuo-Chin Chang ,  Po-Hao Tsai ,  Mirng-Ji Lii

IPC: H01L23/00

Abstract: Semiconductor devices and methods of manufacturing are provided, wherein a first passivation layer is deposited over a top redistribution structure; a second passivation layer is deposited over the first passivation layer; and a first opening is formed through the second passivation layer. After the forming the first opening, the first opening is reshaped into a second opening; a third opening is formed through the first passivation layer; and filling the second opening and the third opening with a conductive material.

公开(公告)号：US11222859B2

公开(公告)日：2022-01-11

申请号：US16866828

申请日：2020-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hao Hsu ,  Wei-Hsiang Tu ,  Kuo-Chin Chang ,  Mirng-Ji Lii

IPC: H01L23/495 ,  H01L23/522 ,  H01L23/00 ,  H01L49/02

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first insulating layer formed over a conductive feature and a capacitor structure embedded in the first insulating layer. The semiconductor device also includes a bonding pad formed over the first insulating layer and corresponding to the capacitor structure. The bonding pad has a top surface and a multi-step edge to form at least three corners. In addition, the semiconductor device structure includes a second insulating layer conformally covering the at least three corners formed by the top surface and the multi-step edge of the bonding pad.

公开(公告)号：US20200328169A1

公开(公告)日：2020-10-15

申请号：US16915780

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Yen-Chang Hu ,  Ching-Wen Hsiao ,  Mirng-Ji Lii ,  Chung-Shi Liu ,  Chien Ling Hwang ,  Chih-Wei Lin ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L23/538

Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.

公开(公告)号：US20200152587A1

公开(公告)日：2020-05-14

申请号：US16733609

申请日：2020-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Ming-Da Cheng ,  Mirng-Ji Lii ,  Meng-Tse Chen ,  Wei-Hung Lin

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/10 ,  H01L23/31 ,  H01L25/03 ,  H01L25/00 ,  H01L23/498 ,  B23K35/00 ,  B23K35/02 ,  B23K35/22 ,  B23K35/26 ,  B23K35/36 ,  H01L25/065

Abstract: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.