公开(公告)号：US11990429B2

公开(公告)日：2024-05-21

申请号：US17994548

申请日：2022-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Kung-Chen Yeh ,  Li-Chung Kuo ,  Pu Wang ,  Szu-Wei Lu

IPC: H01L23/00 ,  H01L21/3105 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L23/562 ,  H01L21/31053 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49827 ,  H01L25/18 ,  H01L25/50

Abstract: A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.

公开(公告)号：US11557568B2

公开(公告)日：2023-01-17

申请号：US16801171

申请日：2020-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01L25/00 ,  H01L21/48 ,  H01L23/48

Abstract: A package includes at least one memory component and an insulating encapsulation. The at least one memory component includes a stacked memory structure and a plurality of conductive posts. The stacked memory structure is laterally encapsulated in a molding compound. The conductive posts are disposed on an upper surface of the stacked memory structure. The upper surface of the stacked memory structure is exposed from the molding compound. The insulating encapsulation encapsulates the at least one memory component. The top surfaces of the conductive posts are exposed form the insulating encapsulation. A material of the molding compound is different a material of the insulating encapsulation.

公开(公告)号：US11145562B2

公开(公告)日：2021-10-12

申请号：US16721829

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hua Chang ,  Chih-Wei Wu ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure includes an interposer, a die and a conductive terminal. The interposer includes an encapsulant substrate, a through via and an interconnection structure. The through via is embedded in the encapsulant substrate. The interconnection structure is disposed on a first side of the encapsulant substrate and electrically connected to the through via. The die is electrically bonded to the interposer and disposed over the interconnection structure and the first side of the encapsulant substrate. The conductive terminal is disposed on a second side of the encapsulant substrate vertically opposite to the first side, and electrically connected to the interposer and the die.

公开(公告)号：US20210098421A1

公开(公告)日：2021-04-01

申请号：US16805865

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/768

Abstract: A package component for carrying a device package and an insulating layer thereon includes a molding layer, first and second redistribution structures disposed on two opposite sides of the molding layer, a semiconductor die, and a through interlayer via (TIV). A hardness of the molding layer is greater than that of the insulating layer that covers the device package. The device package is mounted on the second redistribution structure, and the insulating layer is disposed on the second redistribution structure opposite to the molding layer. The semiconductor die is embedded in the molding layer and electrically coupled to the device package through the second redistribution structure. The TIV penetrates through the molding layer to connect the first and the second redistribution structure. An electronic device and a manufacturing method thereof are also provided.

公开(公告)号：US20210082894A1

公开(公告)日：2021-03-18

申请号：US16572619

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weiming Chris Chen ,  Chi-Hsi Wu ,  Chih-Wei Wu ,  Kuo-Chiang Ting ,  Szu-Wei Lu ,  Shang-Yun Hou ,  Ying-Ching Shih ,  Hsien-Ju Tsou ,  Cheng-Chieh Li

IPC: H01L25/18 ,  H01L23/367 ,  H01L25/00 ,  H01L23/00 ,  H01L21/82 ,  H01L23/48 ,  H01L21/56

Abstract: A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.

公开(公告)号：US10756058B2

公开(公告)日：2020-08-25

申请号：US16116892

申请日：2018-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Ching Shih ,  Chih-Wei Wu ,  Szu-Wei Lu

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first chip, a second chip, self-aligned structures, a bridge structure, and an insulating encapsulant. The first chip has a first rear surface opposite to a first active surface. The second chip is disposed beside the first chip and has a second rear surface opposite to a second active surface. The self-aligned structures are disposed on the first rear surface of the first chip and the second rear surface of the second chip. The bridge structure is electrically connected to the first chip and the second chip. The insulating encapsulant covers at least the side surfaces of the first and second chips, a side surface of the semiconductor substrate, and the side surfaces of the self-aligned structures.

公开(公告)号：US20200035622A1

公开(公告)日：2020-01-30

申请号：US16595741

申请日：2019-10-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/14 ,  H01L23/48 ,  H01L23/498

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure has a first conductive layer on a first substrate and a second conductive layer on a second substrate. A bonding structure is disposed between the first conductive layer and the second conductive layer. A support structure is disposed between the first substrate and the second substrate. A passivation layer covers a bottom surface of the first conductive layer and has a lower surface facing an uppermost surface of the support structure.

公开(公告)号：US20170103954A1

公开(公告)日：2017-04-13

申请号：US15389738

申请日：2016-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/145 ,  H01L23/147 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/10135 ,  H01L2224/11464 ,  H01L2224/13012 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13664 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81139 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Some embodiments of the present disclosure relate to a three dimensional integrated circuit (3DIC) structure. The 3DIC structure has a first die and a second die that is bonded to the first die by one or more bonding structures. The one or more bonding structures respectively have a first metal pad arranged on the first die and a second metal pad arranged on the second die. A first plurality of support structures are disposed between the first die and the second die. The first plurality of support structures include polymers and are laterally spaced apart from a closest one of the one or more bonding structures. The first plurality of support structures extend below an upper surface of the second metal pad.

公开(公告)号：US20230411329A1

公开(公告)日：2023-12-21

申请号：US17929180

申请日：2022-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Wen-Chih Chiou

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/16 ,  H01L2224/11618 ,  H01L2224/16147 ,  H01L24/32 ,  H01L2224/32505 ,  H01L2224/0913 ,  H01L24/09 ,  H01L2224/08147 ,  H01L2224/08146 ,  H01L24/08 ,  H01L24/24 ,  H01L2224/24146 ,  H01L2924/3841 ,  H01L2924/37001

Abstract: A method includes forming a first package component, which comprises forming a first dielectric layer having a first top surface, and forming a first conductive feature. The first conductive feature includes a via embedded in the first dielectric layer, and a metal bump having a second top surface higher than the first top surface of the first dielectric layer. The method further includes dispensing a photo-sensitive layer, with the photo-sensitive layer covering the metal bump, and performing a photolithography process to form a recess in the photo-sensitive layer. The metal bump is exposed to the recess, and the photo-sensitive layer has a third top surface higher than the metal bump. A second package component is bonded to the first package component, and a solder region extends into the recess to bond the metal bump to a second conductive feature in the second package component.

公开(公告)号：US11810831B2

公开(公告)日：2023-11-07

申请号：US17872488

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu

IPC: H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/18 ,  H01L21/822 ,  H01L25/11

CPC classification number: H01L23/3135 ,  H01L21/56 ,  H01L23/18 ,  H01L25/0657 ,  H01L25/50 ,  H01L21/563 ,  H01L21/568 ,  H01L21/8221 ,  H01L25/117 ,  H01L2225/06513

Abstract: An integrated circuit package and a method of forming the same are provided. A method includes stacking a plurality of integrated circuit dies on a wafer to form a die stack. A bonding process is performed on the die stack. The bonding process mechanically and electrically connects adjacent integrated circuit dies of the die stack to each other. A dam structure is formed over the wafer. The dam structure surrounds the die stack. A first encapsulant is formed over the wafer and between the die stack and the dam structure. The first encapsulant fills gaps between the adjacent integrated circuit dies of the die stack. A second encapsulant is formed over the wafer. The second encapsulant surrounds the die stack, the first encapsulant and the dam structure.