公开(公告)号：US12015077B2

公开(公告)日：2024-06-18

申请号：US17676335

申请日：2022-02-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ju-Li Huang ,  Chun-Sheng Liang ,  Ming-Chi Huang ,  Ming-Hsi Yeh ,  Ying-Liang Chuang ,  Hsin-Che Chiang

IPC分类号： H01L29/66 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/02 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/321

CPC分类号： H01L29/66545 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/82345 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/0206 ,  H01L21/02068 ,  H01L21/0276 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/6656 ,  H01L29/66636

摘要： Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.

公开(公告)号：US20230369465A1

公开(公告)日：2023-11-16

申请号：US18356062

申请日：2023-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chih Kao ,  Hsin-Che Chiang ,  Yu-San Chien ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC分类号： H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/033 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/324 ,  H01L21/768

CPC分类号： H01L29/66795 ,  H01L27/0922 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/0337 ,  H01L29/785 ,  H01L29/0649 ,  H01L21/762 ,  H01L21/324 ,  H01L29/66545 ,  H01L21/76832

摘要： An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

公开(公告)号：US11810978B2

公开(公告)日：2023-11-07

申请号：US17339020

申请日：2021-06-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ju-Li Huang ,  Hsin-Che Chiang ,  Yu-Chi Pan ,  Chun-Ming Yang ,  Chun-Sheng Liang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L21/285 ,  H01L29/40 ,  H01L21/3213 ,  H01L29/49

CPC分类号： H01L29/785 ,  H01L21/28556 ,  H01L21/32134 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/4966

摘要： The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.

公开(公告)号：US11799017B2

公开(公告)日：2023-10-24

申请号：US17700812

申请日：2022-03-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chih Kao ,  Hsin-Che Chiang ,  Yu-San Chien ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC分类号： H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/033 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/324 ,  H01L21/768

CPC分类号： H01L29/66795 ,  H01L21/0337 ,  H01L21/324 ,  H01L21/762 ,  H01L21/76832 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

摘要： An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

公开(公告)号：US20230268404A1

公开(公告)日：2023-08-24

申请号：US18309564

申请日：2023-04-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd

发明人： Ming-Chia Tai ,  Ju-Yuan Tzeng ,  Hsin-Che Chiang ,  Yuan-Sheng Huang ,  Chun-Sheng Liang

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L21/3065 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L29/66795 ,  H01L21/3065 ,  H01L27/0886 ,  H01L21/823431 ,  H01L29/785

摘要： A method of applying and then removing a protective layer over a portion of a gate stack is provided. The protective layer is deposited and then a plasma precursor is separated into components. Neutral radicals are then utilized in order to remove the protective layer. In some embodiments the removal also forms a protective by-product which helps to protect underlying layers from damage during the etching process.

公开(公告)号：US11476156B2

公开(公告)日：2022-10-18

申请号：US17001189

申请日：2020-08-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Che Chiang ,  Ju-Li Huang ,  Chun-Sheng Liang ,  Jeng-Ya Yeh

IPC分类号： H01L29/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/417 ,  H01L21/311

摘要： In one exemplary aspect, a method for semiconductor manufacturing comprises forming first and second silicon nitride features on sidewall surfaces of a contact hole, where the contact hole is disposed in a dielectric layer and above a source/drain (S/D) feature. The method further comprises forming a contact plug in the contact hole, the contact plug being electrically coupled to the S/D feature, removing a top portion of the contact plug to create a recess in the contact hole, forming a hard mask layer in the recess, and removing the first and second silicon nitride features via selective etching to form first and second air gaps, respectively.

公开(公告)号：US20210119033A1

公开(公告)日：2021-04-22

申请号：US16656744

申请日：2019-10-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-San Chien ,  Hsin-Che Chiang ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/768

摘要： An embodiment method includes forming a semiconductor liner layer on a first fin structure and on a second fin structure and forming a first capping layer on the semiconductor liner layer disposed on the first fin structure. The method further includes forming a second capping layer on the semiconductor liner layer disposed on the first fin structure, where a composition of the first capping layer is different from a composition of the second capping layer. The method additionally includes performing a thermal process on the first capping layer, the second capping layer, and the semiconductor liner layer to form a first channel region in the first fin structure and a second channel region in the second fin structure. A concentration profile of a material of the first channel region is different from a concentration profile of a material of the second channel region.

公开(公告)号：US20200152521A1

公开(公告)日：2020-05-14

申请号：US16735184

申请日：2020-01-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ju-Li Huang ,  Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Wei-Ze Xu ,  Yueh-Yi Chen ,  Shu-Hui Wang ,  Shih-Hsun Chang

IPC分类号： H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L27/092

摘要： A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.

公开(公告)号：US20190333826A1

公开(公告)日：2019-10-31

申请号：US15966299

申请日：2018-04-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ju-Li Huang ,  Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Wei-Ze Xu ,  Yueh-Yi Chen ,  Shu-Hui Wang ,  Shih-Hsun Chang

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311

摘要： A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.

公开(公告)号：US11923194B2

公开(公告)日：2024-03-05

申请号：US17728369

申请日：2022-04-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Che Chiang ,  Wei-Chih Kao ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L21/0245 ,  H01L21/02507 ,  H01L21/02587 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device includes a semiconductor substrate having a first lattice constant, a dopant blocking layer disposed over the semiconductor substrate, the dopant blocking layer having a second lattice constant different from the first lattice constant, and a buffer layer disposed over the dopant blocking layer, the buffer layer having a third lattice constant different from the second lattice constant. The semiconductor device also includes a plurality of channel members suspended over the buffer layer, an epitaxial feature abutting the channel members, and a gate structure wrapping each of the channel members.