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公开(公告)号：US11784056B2
公开(公告)日：2023-10-10
申请号：US17883930
申请日：2022-08-09
发明人： Kuan-Wei Huang , Yu-Yu Chen , Jyu-Horng Shieh
IPC分类号： H01L21/308 , H01L21/311 , H01L21/768
CPC分类号： H01L21/3085 , H01L21/3088 , H01L21/31144 , H01L21/76802 , H01L21/76898
摘要： A method includes patterning a mandrel layer over a target layer to form first mandrels and second mandrels, the first mandrels having a larger width than the second mandrels. A spacer layer is formed over the first mandrels and the second mandrels, and altered so that a thickness of the spacer layer over the first mandrels is greater than a thickness of the spacer layer over the second mandrels. Spacers are formed from the spacer layer which have a greater width adjacent the first mandrels than the spacers which are adjacent the second mandrels. The spacers are used to etch a target layer.
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公开(公告)号：US11177138B2
公开(公告)日：2021-11-16
申请号：US16837252
申请日：2020-04-01
发明人： Chia-Ying Lee , Jyu-Horng Shieh
IPC分类号： H01L21/311 , H01L21/768 , H01L21/033 , H01L21/027
摘要： The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method includes forming a first hard mask layer over a substrate and forming a second hard mask layer over the first hard mask layer. The second hard mask layer is patterned to define an island having a first width along a first direction. The island is patterned to form a patterned island having a second width along the first direction that is less than the first width. A sacrificial mask is formed over the first hard mask layer and the first hard mask layer is patterned according to the patterned island and the sacrificial mask.
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公开(公告)号：US20210313396A1
公开(公告)日：2021-10-07
申请号：US17346855
申请日：2021-06-14
发明人： Tai-Yen Peng , Tsung-Hsien Chang , Yu-Shu Chen , Chih-Yuan Ting , Jyu-Horng Shieh , Chung-Te Lin
摘要： A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.
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公开(公告)号：US11063217B2
公开(公告)日：2021-07-13
申请号：US16983928
申请日：2020-08-03
发明人： Tai-Yen Peng , Hui-Hsien Wei , Wei-Chih Wen , Pin-Ren Dai , Chien-Min Lee , Han-Ting Tsai , Jyu-Horng Shieh , Chung-Te Lin
摘要： A semiconductor device includes an inter-layer dielectric (ILD) layer, a first metallization pattern, an etch stop layer, a metal-containing compound layer, a memory cell, and a second metallization pattern. The first metallization pattern is in the ILD layer. The etch stop layer is over the ILD layer. The metal-containing compound layer is over the etch stop layer, in which the etch stop layer has a portion extending beyond an edge of the metal-containing compound layer. The memory cell is over the metal-containing compound layer and including a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element. The second metallization pattern extends through the portion of the etch stop layer to the first metallization pattern.
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公开(公告)号：US20190267211A1
公开(公告)日：2019-08-29
申请号：US16177530
申请日：2018-11-01
发明人： Sheng-Liang Pan , Bing-Hung Chen , Chia-Yang Hung , Jyu-Horng Shieh , Shu-Huei Suen , Syun-Ming Jang , Jack Kuo-Ping Kuo
摘要： Embodiments described herein relate to plasma processes. A tool includes a pedestal. The pedestal is configured to support a semiconductor substrate. The tool includes a bias source. The bias source is electrically coupled to the pedestal. The bias source is operable to bias the pedestal with a direct current (DC) voltage. The tool includes a plasma generator. The plasma generator is operable to generate a plasma remote from the pedestal. A method for semiconductor processing includes performing a plasma process on a substrate in a tool. The plasma process includes flowing a gas into the tool. The plasma process includes biasing a pedestal that supports the substrate in the tool. The plasma process includes igniting a plasma in the tool using the gas.
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公开(公告)号：US10276376B2
公开(公告)日：2019-04-30
申请号：US14636219
申请日：2015-03-03
发明人： Chia-Ying Lee , Jyu-Horng Shieh
IPC分类号： H01L21/311 , H01L21/033 , H01L21/768
摘要： A multi-patterning method includes: patterning at least two first openings in a hard mask layer over a substrate using a first mask; forming spacers within two of the at least two first openings, each spacer having a spacer opening therein for patterning a respective first circuit pattern over the substrate, wherein each spacer defines a pattern-free region adjacent to a respective one of the at least two first circuit patterns, and patterning a second circuit pattern in the hard mask layer using a second mask. The second circuit pattern is located between and excluded from the pattern free regions adjacent the at least two first circuit patterns.
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公开(公告)号：US09711372B2
公开(公告)日：2017-07-18
申请号：US14935792
申请日：2015-11-09
发明人： Chia-Ying Lee , Jyu-Horng Shieh
IPC分类号： H01L21/302 , H01L21/311 , H01L21/768 , H01L21/033 , H01L21/027
CPC分类号： H01L21/31144 , H01L21/027 , H01L21/0337 , H01L21/76816 , H01L21/76832 , H01L21/76883
摘要： In some embodiments, the disclosure relates to a method of forming an integrated circuit device. The method is performed by forming a first mask layer over a substrate and a second mask layer over the first mask layer. The second mask layer is patterned to form cut regions. A mandrel is formed over the first mask layer and the cut regions, and the first mask layer is etched using the mandrel form a patterned first mask. The substrate is etched according to the patterned first mask and the cut regions to form trenches in the substrate, and the trenches are filled with conductive metal to form conductive lines.
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公开(公告)号：US12127489B2
公开(公告)日：2024-10-22
申请号：US18170947
申请日：2023-02-17
发明人： Tai-Yen Peng , Hui-Hsien Wei , Wei-Chih Wen , Pin-Ren Dai , Chien-Min Lee , Han-Ting Tsai , Jyu-Horng Shieh , Chung-Te Lin
CPC分类号： H10N70/884 , H10B61/22 , H10B63/30 , H10B63/82 , H10B63/84 , H10N50/01 , H10N50/80 , H10N70/023 , H10N70/063 , H10N70/24 , H10N70/245 , H10N70/826 , H10N70/8416 , H10N70/8833
摘要： An IC structure comprises a substrate, a first dielectric structure, a second dielectric structure, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first dielectric structure is over the memory region. The second dielectric structure laterally extends from the first dielectric structure to over the logic region. The second dielectric structure has a thickness less than a thickness of the first dielectric structure. The first via structure extends through the first dielectric structure. A top segment of the first via structure is higher than a top surface of the first dielectric structure. The first memory cell structure is over the first via structure.
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公开(公告)号：US20240099150A1
公开(公告)日：2024-03-21
申请号：US18521399
申请日：2023-11-28
发明人： Tai-Yen Peng , Yu-Shu Chen , Sin-Yi Yang , Chen-Jung Wang , Chien Chung Huang , Han-Ting Lin , Jyu-Horng Shieh , Qiang Fu
摘要： A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
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公开(公告)号：US11796922B2
公开(公告)日：2023-10-24
申请号：US16587710
申请日：2019-09-30
发明人： Ru-Gun Liu , Huicheng Chang , Chia-Cheng Chen , Jyu-Horng Shieh , Liang-Yin Chen , Shu-Huei Suen , Wei-Liang Lin , Ya Hui Chang , Yi-Nien Su , Yung-Sung Yen , Chia-Fong Chang , Ya-Wen Yeh , Yu-Tien Shen
CPC分类号： G03F7/70558 , G03F1/22 , G03F1/36 , G03F1/70 , G03F7/0035 , G03F7/40 , G03F7/70033 , G03F7/70625 , H01L21/0274
摘要： In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.
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