公开(公告)号：US10084032B2

公开(公告)日：2018-09-25

申请号：US15582963

申请日：2017-05-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Li Huang ,  Chi-Cheng Chen ,  Hon-Lin Huang ,  Chien-Chih Chou ,  Chin-Yu Ku ,  Chen-Shien Chen

IPC分类号： H01L21/311 ,  H01L21/3213 ,  H01L49/02 ,  H01F41/04 ,  H01F27/28 ,  H01L27/22 ,  H01L23/522 ,  H01L23/64

CPC分类号： H01L28/10 ,  H01F27/2804 ,  H01F41/041 ,  H01L21/32134 ,  H01L21/32138 ,  H01L21/32139 ,  H01L23/5227 ,  H01L23/645 ,  H01L27/222 ,  H01L2924/1206

摘要： A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material.

公开(公告)号：US09349699B2

公开(公告)日：2016-05-24

申请号：US14257734

申请日：2014-04-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hon-Lin Huang ,  Ching-Wen Hsiao ,  Kuo-Ching Hsu ,  Chen-Shien Chen

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/48

CPC分类号： H01L24/11 ,  H01L23/3157 ,  H01L23/481 ,  H01L24/13 ,  H01L24/81 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/11823 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11912 ,  H01L2224/13027 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/818 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/05552

摘要： A method of forming an integrated circuit structure is provided. The method includes providing a substrate, the substrate having a conductive pad thereon. A dielectric buffer layer is formed over at least a portion of the conductive pad, and an under-bump-metallurgy (UBM) is formed directly coupled to the conductive pad, wherein the UBM extends over at least a portion of the dielectric buffer layer. Thereafter, a conductive pillar is formed over the UBM, and one or more conductive materials are formed over the conductive pillar. The substrate may be attached to a carrier substrate using an adhesive.

摘要翻译： 提供一种形成集成电路结构的方法。 所述方法包括提供衬底，所述衬底在其上具有导电垫。 在导电焊盘的至少一部分上形成介电缓冲层，并且形成直接耦合到导电焊盘的凸起下冶金（UBM），其中UBM延伸至介电缓冲层的至少一部分。 此后，在UBM上形成导电柱，并且在导电柱上方形成一个或多个导电材料。 衬底可以使用粘合剂附接到载体衬底。

公开(公告)号：US09190347B2

公开(公告)日：2015-11-17

申请号：US13967165

申请日：2013-08-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jen Lai ,  You-Hua Chou ,  Hon-Lin Huang ,  Huai-Tei Yang

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/18

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/03823 ,  H01L2224/03825 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05009 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05655 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/01046 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like.

摘要翻译： 提供了利用芯片边缘触点的半导体器件。 集成电路管芯具有后钝化层，其具有填充有从接触件延伸到管芯边缘的导电材料的沟槽，从而形成管芯边缘接触。 可选地，贯穿衬底通孔可以沿着管芯边缘定位，使得沟槽中的导电材料电连接到贯穿衬底通孔，从而形成更大的管芯边缘接触。 集成电路管芯可以放置在多管芯封装中，其中多管芯封装包括具有垂直于集成电路管芯的主表面的主表面的壁。 模边缘触点电耦合到多模封装的壁上的触点。 多管芯封装可以包括用于连接到另一衬底的边缘触点，例如印刷电路板，封装衬底，高密度互连等。

公开(公告)号：US20190267445A1

公开(公告)日：2019-08-29

申请号：US16410440

申请日：2019-05-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Li Huang ,  Chi-Cheng Chen ,  Hon-Lin Huang ,  Chien-Chih Chou ,  Chin-Yu Ku ,  Chen-Shien Chen

IPC分类号： H01L49/02 ,  H01L21/3213 ,  H01F41/04 ,  H01F27/28 ,  H01L27/22 ,  H01L23/64 ,  H01L23/522

摘要： A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material.

公开(公告)号：US20190027553A1

公开(公告)日：2019-01-24

申请号：US16139682

申请日：2018-09-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Li Huang ,  Chi-Cheng Chen ,  Hon-Lin Huang ,  Chien-Chih Chou ,  Chin-Yu Ku ,  Chen-Shien Chen

IPC分类号： H01L49/02 ,  H01F27/28 ,  H01F41/04 ,  H01L21/3213 ,  H01L27/22 ,  H01L23/64 ,  H01L23/522

摘要： A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material.

公开(公告)号：US20130328215A1

公开(公告)日：2013-12-12

申请号：US13967165

申请日：2013-08-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jen Lai ,  You-Hua Chou ,  Hon-Lin Huang ,  Huai-Tei Yang

IPC分类号： H01L23/48

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/03823 ,  H01L2224/03825 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05009 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05655 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/01046 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like.

摘要翻译： 提供了利用芯片边缘触点的半导体器件。 集成电路管芯具有后钝化层，其具有填充有从接触件延伸到管芯边缘的导电材料的沟槽，从而形成管芯边缘接触。 可选地，贯穿衬底通孔可以沿着管芯边缘定位，使得沟槽中的导电材料电连接到贯穿衬底通孔，从而形成更大的管芯边缘接触。 集成电路管芯可以放置在多管芯封装中，其中多管芯封装包括具有垂直于集成电路管芯的主表面的主表面的壁。 模边缘触点电耦合到多模封装的壁上的触点。 多管芯封装可以包括用于连接到另一衬底的边缘触点，例如印刷电路板，封装衬底，高密度互连等。

公开(公告)号：US12074193B2

公开(公告)日：2024-08-27

申请号：US18193544

申请日：2023-03-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chi-Cheng Chen ,  Wei-Li Huang ,  Chun-Yi Wu ,  Kuang-Yi Wu ,  Hon-Lin Huang ,  Chih-Hung Su ,  Chin-Yu Ku ,  Chen-Shien Chen

IPC分类号： H01L23/31 ,  H01F41/04 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L49/02

CPC分类号： H01L28/10 ,  H01F41/046 ,  H01L21/76823 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/53204 ,  H01L24/05 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The semiconductor device structure also includes an isolation layer extending exceeding edges the magnetic element. The isolation layer contains a polymer material. The semiconductor device structure further includes a conductive line over the isolation layer and extending exceeding the edges of the magnetic element.

公开(公告)号：US12057468B2

公开(公告)日：2024-08-06

申请号：US17144121

申请日：2021-01-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Hsien Kuo ,  Hon-Lin Huang ,  Han-Yi Lu ,  Ching-Wen Hsiao ,  Alexander Kalnitsky

IPC分类号： H01F17/00 ,  H01F17/04 ,  H01F41/04 ,  H01L49/02

CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01F17/0033 ,  H01F17/04 ,  H01F41/046 ,  H01F2017/0086

摘要： An inductor includes a core and a conductive spiral wound around the core. The core includes a buffer layer, an etch stop layer, and a core material layer sequentially stacked. The core material layer includes a ferromagnetic material. A total area of a vertical projection of the core material layer is smaller than an area occupied by the etch stop layer. The vertical projection of the core material layer falls entirely on the etch stop layer. The etch stop layer horizontally protrudes with respect to the core material layer.

公开(公告)号：US20220384220A1

公开(公告)日：2022-12-01

申请号：US17885488

申请日：2022-08-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Wei Lu ,  Hon-Lin Huang ,  Hung-Chih Wang

IPC分类号： H01L21/67 ,  C23C18/16 ,  B05C11/06 ,  H01L21/673

摘要： A semiconductor processing station includes first and second chambers, and a cooling stage. The second chamber includes a cooling pipe disposed inside the second chamber, and an external pipe. The cooling pipe includes a first segment disposed along a sidewall of the second chamber, and a second segment disposed perpendicular to the first segment and located above a wafer carrier in the second chamber. An end of the second segment is connected to an end of the first segment. The external pipe is connected to the second segment distal from the end of the second segment to provide a fluid to flow through the cooling pipe from an exterior to an interior of the second chamber. The fluid discharges toward the wafer carrier through the first segment. The first chamber is surrounded by the second chamber and the cooling stage, and communicates between the cooling stage and the second chamber.

公开(公告)号：US20220216295A1

公开(公告)日：2022-07-07

申请号：US17144121

申请日：2021-01-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Hsien Kuo ,  Hon-Lin Huang ,  Han-Yi Lu ,  Ching-Wen Hsiao ,  Alexander Kalnitsky

IPC分类号： H01L49/02 ,  H01F17/00 ,  H01F41/04 ,  H01F17/04

摘要： An inductor includes a core and a conductive spiral wound around the core. The core includes a buffer layer, an etch stop layer, and a core material layer sequentially stacked. The core material layer includes a ferromagnetic material. A total area of a vertical projection of the core material layer is smaller than an area occupied by the etch stop layer. The vertical projection of the core material layer falls entirely on the etch stop layer. The etch stop layer horizontally protrudes with respect to the core material layer.