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    Method for leakage reduction in fabrication of high-density FRAM arrays
    12.
    发明授权
    Method for leakage reduction in fabrication of high-density FRAM arrays 有权
    高密度FRAM阵列制造中泄漏减少的方法

    公开(公告)号：US08093070B2

    公开(公告)日：2012-01-10

    申请号：US11706722

    申请日：2007-02-15

    Applicant: Francis Gabriel Celii ,  Kezhakkedath R. Udayakumar ,  Gregory B. Shinn ,  Theodore S. Moise ,  Scott R. Summerfelt

    Inventor： Francis Gabriel Celii ,  Kezhakkedath R. Udayakumar ,  Gregory B. Shinn ,  Theodore S. Moise ,  Scott R. Summerfelt

    IPC: H01L21/00

    CPC classification number: H01L28/75 ,  H01L27/11507 ,  H01L28/55

    Abstract: A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.

    Abstract translation: 提供一种用于制造铁电电容器结构的方法，其包括在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法。 该方法包括蚀刻上电极的部分，蚀刻铁电材料，并蚀刻下电极以限定图案化的铁电电容器结构，以及蚀刻下电极扩散阻挡结构的一部分。 所述方法还包括使用第一灰化过程灰化所述图案化的铁电电容器结构，其中所述灰分包括含氧/氮/水的灰分，在所述第一灰化处理之后执行湿式清洁处理，以及使用 第二次灰化过程。

    Programmable reference for 1T/1C ferroelectric memories
    14.
    发明授权
    Programmable reference for 1T/1C ferroelectric memories 有权

    公开(公告)号：US06819601B2

    公开(公告)日：2004-11-16

    申请号：US10454862

    申请日：2003-06-05

    Applicant: Jarrod Eliason ,  Bill Kraus ,  Hugh McAdams ,  Scott Summerfelt ,  Theodore S. Moise

    Inventor： Jarrod Eliason ,  Bill Kraus ,  Hugh McAdams ,  Scott Summerfelt ,  Theodore S. Moise

    IPC: G11C700

    CPC classification number: G11C11/22

    Abstract: A ferroelectric memory device is disclosed and comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one or more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereto for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and the reference voltage on the second bit line.

    Ultrascaled MIS transistors fabricated using silicon-on-lattice-matched insulator approach
    15.
    发明授权
    Ultrascaled MIS transistors fabricated using silicon-on-lattice-matched insulator approach 有权
    使用硅 - 晶格匹配绝缘子方法制造的超平面MIS晶体管

    公开(公告)号：US06534348B1

    公开(公告)日：2003-03-18

    申请号：US09292063

    申请日：1999-04-14

    Applicant: Theodore S. Moise ,  Glen D. Wilk

    Inventor： Theodore S. Moise ,  Glen D. Wilk

    IPC: H01L2100

    CPC classification number: H01L29/4908 ,  H01L29/045 ,  H01L29/66772 ,  H01L29/78648 ,  H01L29/78654

    Abstract: A method of fabricating a transistor using silicon on lattice matched insulator. A first monocrystalline silicon layer is provided and a first layer of dielectric is epitaxially deposited over the first silicon layer substantially lattice matched with the first silicon layer and substantially monocrystalline. A first electrically conductive gate electrode is epitaxially formed over the first layer of dielectric substantially lattice matched with the first layer of dielectric. A second layer of dielectric is epitaxially deposited conformally over the first gate electrode and exposed portions of first layer of dielectric substantially lattice matched with the first silicon layer and substantially monocrystalline. A second monocrystalline silicon layer is epitaxially deposited over the second layer of dielectric and a third layer of dielectric is epitaxially deposited over the second silicon layer substantially lattice matched with the first silicon layer and substantially monocrystalline. A second electrically conductive gate electrode is epitaxially deposited and formed over the third layer of dielectric which is substantially lattice matched with the first silicon layer and the first layer of dielectric. Source and drain regions are formed in the second silicon layer.

    Abstract translation: 在晶格匹配绝缘体上制造使用硅的晶体管的方法。 提供第一单晶硅层，并且第一层电介质外延沉积在基本上与第一硅层晶格匹配并且基本上单晶的第一硅层上。 第一导电栅极电极外延形成在基本上与第一电介质层晶格匹配的电介质的第一层上。 电介质的第二层被外延地平铺地沉积在第一栅极电极上，并且第一介电层的暴露部分基本上与第一硅层晶格匹配并且基本上是单晶的。 第二单晶硅层外延沉积在第二层电介质上，并且第三层电介质外延沉积在第二硅层上，基本上与第一硅层基本上晶格匹配并且基本上是单晶。 第二导电栅电极被外延沉积并形成在与第一硅层和第一介电层基本上晶格匹配的第三电介质层上。 源极和漏极区域形成在第二硅层中。

    Ferroelectric transistors using thin film semiconductor gate electrodes
    16.
    发明授权
    Ferroelectric transistors using thin film semiconductor gate electrodes 有权
    使用薄膜半导体栅电极的铁电晶体管

    公开(公告)号：US06362499B1

    公开(公告)日：2002-03-26

    申请号：US09645158

    申请日：2000-08-24

    Applicant: Theodore S. Moise ,  Scott R. Summerfelt

    Inventor： Theodore S. Moise ,  Scott R. Summerfelt

    IPC: H01L2976

    CPC classification number: G11C29/44 ,  G11C11/223 ,  G11C2029/1208 ,  H01L21/28291 ,  H01L29/78391

    Abstract: A ferroelectric structure on an integrated circuit and methods of making and using the same are disclosed, which may be used, for instance, in a high-speed, non-volatile, non-destructive readout random-access memory device. Generally, the ferroelectric structure combines a thin film ferroelectric variable resistor and a substrate (e.g. silicon) transistor, using a semiconducting film which is common to both. A field effect transistor 26 integrated into substrate 30 has a gate oxide 36 and a semiconducting gate electrode 38 with electrical connections at a first end 44 and a second end 46. Overlying gate electrode 38 is a ferroelectric thin film 40 and a conductive electrode 42. The polarization of ferroelectric thin film 40 is set by applying an appropriate voltage between gate electrode 38 and conductive electrode 42. The polarization of ferroelectric thin film 40 may be subsequently determined by applying a read voltage to 42 and 44, thus causing a voltage V2 to appear at 46 which is determined by the polarization of the ferroelectric variable resistor formed by 38 and 40. Since 38 also forms the gate electrode for field effect transistor 26, the magnitude of V2 affects the magnitude of current I2. Thus I2 is effectively an amplified signal related to the ferroelectric variable resistance which may be read without perturbing the polarization of ferroelectric thin film 40.

    Abstract translation: 公开了集成电路中的铁电结构及其制造和使用的方法，其可以用于例如高速，非易失性，非破坏性读出随机存取存储器件中。 通常，铁电结构使用两者共同的半导体膜组合薄膜铁电可变电阻器和衬底（例如硅）晶体管。 集成到基板30中的场效应晶体管26具有在第一端44和第二端46具有电连接的栅极氧化物36和半导体栅电极38.叠层栅电极38是铁电薄膜40和导电电极42。 通过在栅电极38和导电电极42之间施加适当的电压来设定铁电薄膜40的极化。随后可以通过将读电压施加到42和44来确定铁电薄膜40的极化，从而使电压V2 出现在46处，其由38和40形成的铁电可变电阻器的极化决定。由于38还形成场效应晶体管26的栅电极，因此V2的大小影响电流I2的大小。 因此，I2实际上是与铁电可变电阻相关的放大信号，其可以在不扰乱铁电薄膜40的极化的情况下读取。

    Ferroelectric transistors using thin film semiconductor gate electrodes
    17.
    发明授权
    Ferroelectric transistors using thin film semiconductor gate electrodes 失效
    使用薄膜半导体栅电极的铁电晶体管

    公开(公告)号：US06225655B1

    公开(公告)日：2001-05-01

    申请号：US08953947

    申请日：1997-10-20

    Applicant: Theodore S. Moise ,  Scott R. Summerfelt

    Inventor： Theodore S. Moise ,  Scott R. Summerfelt

    IPC: H01L2976

    CPC classification number: G11C29/44 ,  G11C11/223 ,  G11C2029/1208 ,  H01L21/28291 ,  H01L29/78391

    Abstract: A ferroelectric structure on an integrated circuit is disclosed, which may be used, for instance, in a high-speed, non-volatile, non-destructive readout random-access memory device. Generally, the ferroelectric structure combines a thin film ferroelectric variable resistor and a substrate (e.g. silicon) transistor, using a semiconducting film which is common to both. A field effect transistor 26 integrated into substrate 30 has a gate oxide 36 and a semiconducting gate electrode 38 with electrical connections at a first end 44 and a second end 46. Overlying gate electrode 38 is a ferroelectric thin film 40 and a conductive electrode 42. The polarization of ferroelectric thin film 40 is set by applying an appropriate voltage between gate electrode 38 and conductive electrode 42. The polarization of ferroelectric thin film 40 may be subsequently determined by applying a read voltage to 42 and 44, thus causing a voltage V2 to appear at 46 which is determined by the polarization of the ferroelectric variable resistor formed by 38 and 40. Since 38 also forms the gate electrode for field effect transistor 26, the magnitude of V2 affects the magnitude of current I2. Thus I2 is effectively an amplified signal related to the ferroelectric variable resistance which may be read without perturbing the polarization of ferroelectric thin film 40.

    Abstract translation: 公开了集成电路中的铁电结构，其可以用于例如高速，非易失性，非破坏性读出随机存取存储器件中。 通常，铁电结构使用两者共同的半导体膜组合薄膜铁电可变电阻器和衬底（例如硅）晶体管。 集成到基板30中的场效应晶体管26具有在第一端44和第二端46具有电连接的栅极氧化物36和半导体栅电极38.叠层栅电极38是铁电薄膜40和导电电极42。 通过在栅电极38和导电电极42之间施加适当的电压来设定铁电薄膜40的极化。随后可以通过将读电压施加到42和44来确定铁电薄膜40的极化，从而使电压V2 出现在46处，其由38和40形成的铁电可变电阻器的极化决定。由于38还形成场效应晶体管26的栅电极，因此V2的大小影响电流I2的大小。 因此，I2实际上是与铁电可变电阻相关的放大信号，其可以在不扰乱铁电薄膜40的极化的情况下读取。

    Method for forming high-density integrated circuit capacitors
    18.
    发明授权
    Method for forming high-density integrated circuit capacitors 有权
    高密度集成电路电容器的形成方法

    公开(公告)号：US06171970B2

    公开(公告)日：2001-01-09

    申请号：US09238211

    申请日：1999-01-27

    Applicant: Guoqiang Xing ,  Abbas Ali ,  Theodore S. Moise

    Inventor： Guoqiang Xing ,  Abbas Ali ,  Theodore S. Moise

    IPC: H01L213065

    CPC classification number: H01L28/55 ,  H01L21/0332 ,  H01L21/32 ,  H01L21/32139 ,  H01L27/10814

    Abstract: A method for etching a platinum surface 200. The method includes the step of forming a hardmask 202 including titanium, aluminum, and nitrogen on the platinum surface. The hardmask covers portions of the platinum surface. The method further includes removing platinum from uncovered portions of the surface with a plasma including a nitrogen-bearing species. The etch chemistry may also comprise an oxygen-bearing species.

    Abstract translation: 一种用于蚀刻铂表面200的方法。该方法包括在铂表面上形成包括钛，铝和氮的硬掩模202的步骤。 硬掩模覆盖铂表面的部分。 该方法还包括用包括含氮物质的等离子体从表面的未覆盖部分去除铂。 蚀刻化学物质也可以包含含氧物质。

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