公开(公告)号：US08872345B2

公开(公告)日：2014-10-28

申请号：US13178079

申请日：2011-07-07

申请人： Chi-Chun Hsieh ,  Wei-Cheng Wu ,  Hsiao-Tsung Yen ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Shin-Puu Jeng

发明人： Chi-Chun Hsieh ,  Wei-Cheng Wu ,  Hsiao-Tsung Yen ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC分类号： H01L23/48 ,  H01L21/283 ,  H01L21/74

CPC分类号： H01L23/481 ,  H01L21/743 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method of forming an interposer includes providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface; forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate; forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and forming an interconnect structure in the ILD layer, the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate.

摘要翻译： 形成插入件的方法包括提供半导体衬底，该半导体衬底具有与前表面相对的前表面和后表面; 形成从所述前表面延伸到所述半导体衬底中的一个或多个穿硅通孔（TSV）; 形成覆盖所述半导体衬底的前表面和所述一个或多个TSV的层间介电层（ILD）层; 以及在所述ILD层中形成互连结构，所述互连结构将所述一个或多个TSV电连接到所述半导体衬底。

公开(公告)号：US20130120018A1

公开(公告)日：2013-05-16

申请号：US13297779

申请日：2011-11-16

申请人： Shang-Yun Hou ,  Wei-Cheng Wu ,  Hsien-Pin Hu ,  Jung Cheng Ko ,  Shin-Puu Jeng ,  Chen-Hua Yu ,  Kim Hong Chen

发明人： Shang-Yun Hou ,  Wei-Cheng Wu ,  Hsien-Pin Hu ,  Jung Cheng Ko ,  Shin-Puu Jeng ,  Chen-Hua Yu ,  Kim Hong Chen

IPC分类号： G01R31/26 ,  H01L23/48 ,  H01L21/58

CPC分类号： H05K1/115 ,  H01L21/76898 ,  H01L22/14 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/1147 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H05K1/0298 ,  H05K2201/2081 ,  H01L2924/01082 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be test by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV.

公开(公告)号：US08105875B1

公开(公告)日：2012-01-31

申请号：US12904835

申请日：2010-10-14

申请人： Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

发明人： Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

IPC分类号： H01L21/50

CPC分类号： H01L21/561 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

摘要翻译： 一种方法包括提供包括衬底的中介层晶片，以及从衬底的前表面延伸到衬底中的多个贯通衬底通孔（TSV）。 多个管芯结合到插入件晶片的前表面上。 在结合多个模具的步骤之后，在基板的背面进行研磨以暴露多个TSV。 多个金属凸块形成在插入器晶片的背面并电耦合到多个TSV。

公开(公告)号：US08319349B2

公开(公告)日：2012-11-27

申请号：US13342583

申请日：2012-01-03

申请人： Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

发明人： Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

IPC分类号： H01L23/48

CPC分类号： H01L21/561 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

公开(公告)号：US20120104578A1

公开(公告)日：2012-05-03

申请号：US13342583

申请日：2012-01-03

申请人： Hsien-Pin Hu ,  Chen-Hu Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

发明人： Hsien-Pin Hu ,  Chen-Hu Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

IPC分类号： H01L23/495

CPC分类号： H01L21/561 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

摘要翻译： 一种方法包括提供包括衬底的中介层晶片，以及从衬底的前表面延伸到衬底中的多个贯通衬底通孔（TSV）。 多个管芯结合到插入件晶片的前表面上。 在结合多个模具的步骤之后，在基板的背面进行研磨以暴露多个TSV。 多个金属凸块形成在插入器晶片的背面并电耦合到多个TSV。

公开(公告)号：US08759150B2

公开(公告)日：2014-06-24

申请号：US13488188

申请日：2012-06-04

申请人： Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

发明人： Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

IPC分类号： H01L21/50

CPC分类号： H01L21/561 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

摘要翻译： 一种方法包括提供包括衬底的中介层晶片，以及从衬底的前表面延伸到衬底中的多个贯通衬底通孔（TSV）。 多个管芯结合到插入件晶片的前表面上。 在结合多个模具的步骤之后，在基板的背面进行研磨以暴露多个TSV。 多个金属凸块形成在插入器晶片的背面并电耦合到多个TSV。

公开(公告)号：US20120238057A1

公开(公告)日：2012-09-20

申请号：US13488188

申请日：2012-06-04

申请人： Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

发明人： Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

IPC分类号： H01L21/60

CPC分类号： H01L21/561 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

公开(公告)号：US08502338B2

公开(公告)日：2013-08-06

申请号：US12878803

申请日：2010-09-09

申请人： Hsiao-Tsung Yen ,  Hsien-Pin Hu ,  Chin-Wei Kuo ,  Sally Liu

发明人： Hsiao-Tsung Yen ,  Hsien-Pin Hu ,  Chin-Wei Kuo ,  Sally Liu

IPC分类号： H01L29/00

CPC分类号： H01L27/0296 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/60 ,  H01L29/861 ,  H01L2223/6622 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014

摘要： A device includes a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a first surface and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the semiconductor substrate. A well region of a second conductivity type opposite the first conductivity type encircles the TSV, and extends from the first surface to the second surface of the semiconductor substrate.

摘要翻译： 一种器件包括第一导电类型的半导体衬底，其中半导体衬底包括与第一表面相对的第一表面和第二表面。 贯穿基板通孔（TSV）从半导体基板的第一表面延伸到第二表面。 与第一导电类型相反的第二导电类型的阱区域包围TSV，并且从半导体衬底的第一表面延伸到第二表面。

公开(公告)号：US20120061795A1

公开(公告)日：2012-03-15

申请号：US12878803

申请日：2010-09-09

申请人： Hsiao-Tsung Yen ,  Hsien-Pin Hu ,  Chin-Wei Kuo ,  Sally Liu

发明人： Hsiao-Tsung Yen ,  Hsien-Pin Hu ,  Chin-Wei Kuo ,  Sally Liu

IPC分类号： H01L29/92 ,  H01L21/265

CPC分类号： H01L27/0296 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/60 ,  H01L29/861 ,  H01L2223/6622 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014

摘要： A device includes a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a first surface and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the semiconductor substrate. A well region of a second conductivity type opposite the first conductivity type encircles the TSV, and extends from the first surface to the second surface of the semiconductor substrate.

摘要翻译： 一种器件包括第一导电类型的半导体衬底，其中半导体衬底包括与第一表面相对的第一表面和第二表面。 贯穿基板通孔（TSV）从半导体基板的第一表面延伸到第二表面。 与第一导电类型相反的第二导电类型的阱区域包围TSV，并且从半导体衬底的第一表面延伸到第二表面。

公开(公告)号：US08471358B2

公开(公告)日：2013-06-25

申请号：US12791705

申请日：2010-06-01

申请人： Hsiao-Tsung Yen ,  Chin-Wei Kuo ,  Hsien-Pin Hu ,  Sally Liu ,  Ming-Fa Chen ,  Jhe-Ching Lu

发明人： Hsiao-Tsung Yen ,  Chin-Wei Kuo ,  Hsien-Pin Hu ,  Sally Liu ,  Ming-Fa Chen ,  Jhe-Ching Lu

IPC分类号： H01L27/08

CPC分类号： H01L23/5227 ,  H01F17/0013 ,  H01F27/2804 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/00 ,  H01L2224/0401

摘要： In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.

摘要翻译： 根据实施例，半导体器件包括半导体管芯，插入件和将半导体管芯接合到插入件的导电凸块。 半导体管芯包括第一金属化层，第一金属化层包括第一导电图案。 插入器包括第二金属化层，并且第二金属化层包括第二导电图案。 一些导电凸块将第一导电图案电耦合到第二导电图案以形成线圈。 其他实施例考虑了线圈，电感器和/或变压器的其他配置，并考虑了制造方法。