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    SEMICONDUCTOR DEVICE
    11.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220406904A1

    公开(公告)日：2022-12-22

    申请号：US17895066

    申请日：2022-08-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yi-Chieh Wang ,  Po-Chun Lai ,  Ke-Feng Lin ,  Chen-An Kuo ,  Ze-Wei Jhou

    IPC: H01L29/40 ,  H01L27/088 ,  H01L29/78

    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

    Semiconductor structure and method for manufacturing the same
    12.
    发明授权
    Semiconductor structure and method for manufacturing the same 有权
    半导体结构及其制造方法

    公开(公告)号：US09236471B2

    公开(公告)日：2016-01-12

    申请号：US14253365

    申请日：2014-04-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chiu-Te Lee ,  Ke-Feng Lin ,  Shu-Wen Lin ,  Kun-Huang Yu ,  Chih-Chung Wang ,  Te-Yuan Wu

    IPC: H01L29/76 ,  H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08

    CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/407

    Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation. The bottom surface of the second portion of the conductive plug is covered by the isolation.

    Abstract translation: 半导体结构包括具有第一导电类型的衬底; 在衬底中形成有第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插头，其包括彼此电连接的第一部分和第二部分，并且所述第一部分电连接到所述栅电极，并且所述第二部分穿透所述隔离。 导电插头的第二部分的底表面被隔离层覆盖。

    METHOD OF FABRICATING HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE
    13.
    发明申请
    METHOD OF FABRICATING HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE 有权
    制造高压金属氧化物半导体晶体管器件的方法

    公开(公告)号：US20150079754A1

    公开(公告)日：2015-03-19

    申请号：US14548248

    申请日：2014-11-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Chung Wang ,  Wei-Lun Hsu ,  Shan-Shi Huang ,  Ke-Feng Lin ,  Te-Yuan Wu

    IPC: H01L29/66 ,  H01L21/033 ,  H01L29/08 ,  H01L21/266 ,  H01L29/40 ,  H01L29/06

    CPC classification number: H01L29/66681 ,  H01L21/0334 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7816

    Abstract: The present invention provides a method of fabricating a HV MOS transistor device, including forming a deep well in a substrate, and the deep well; forming a first doped region in the deep well, and the first doped region, wherein a doping concentration of the first doped region and a doping concentration of the deep well in at least one electric field concentration region has a first ratio, the doping concentration of the first doped region and the doping concentration of the deep well outside the electric field concentration region has a second ratio, and the first ratio is greater than the second ratio; and forming a high voltage well in the substrate, and forming a second doped region and a third doped region respectively in the deep well and in the high voltage well.

    Abstract translation: 本发明提供一种制造HV MOS晶体管器件的方法，包括在衬底和深阱中形成深阱; 在所述深阱中形成第一掺杂区域和所述第一掺杂区域，其中所述第一掺杂区域的掺杂浓度和所述深阱在至少一个电场浓度区域中的掺杂浓度具有第一比率，所述第一掺杂区域的掺杂浓度 第一掺杂区域和电场浓度区外的深阱的掺杂浓度具有第二比例，第一比值大于第二比例; 以及在所述衬底中形成高电压阱，以及分别在所述深阱和所述高电压阱中形成第二掺杂区和第三掺杂区。

    High voltage metal-oxide-semiconductor transistor device
    14.
    发明授权
    High voltage metal-oxide-semiconductor transistor device 有权
    高压金属氧化物半导体晶体管器件

    公开(公告)号：US08921972B2

    公开(公告)日：2014-12-30

    申请号：US13896289

    申请日：2013-05-16

    Applicant: United Microelectronics Corp.

    Inventor： Ming-Shun Hsu ,  Ke-Feng Lin ,  Chiu-Te Lee ,  Chih-Chung Wang

    IPC: H01L21/70 ,  H01L29/78 ,  H01L27/092 ,  H01L27/085 ,  H01L27/088

    CPC classification number: H01L29/7816 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/085 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878

    Abstract: A high voltage metal-oxide-semiconductor (HV MOS) transistor device includes a substrate, a drifting region formed in the substrate, a plurality of isolation structures formed in the drift region and spaced apart from each other by the drift region, a plurality of doped islands respectively formed in the isolation structures, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective two sides of the gate. The gate covers a portion of each isolation structure. The drift region, the source region, and the drain region include a first conductivity type, the doped islands include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

    Abstract translation: 高压金属氧化物半导体（HV MOS）晶体管器件包括衬底，形成在衬底中的漂移区域，形成在漂移区域中并由漂移区域彼此分开的多个隔离结构，多个 分别形成在隔离结构中的掺杂岛，形成在衬底上的栅极，以及在栅极的相应两侧形成在衬底中的源极区和漏极区。 门覆盖每个隔离结构的一部分。 漂移区域，源区域和漏极区域包括第一导电类型，掺杂岛包括第二导电类型，并且第一导电类型和第二导电类型彼此互补。

    HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE
    15.
    发明申请
    HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE 有权
    高电压金属氧化物半导体晶体管器件

    公开(公告)号：US20140091369A1

    公开(公告)日：2014-04-03

    申请号：US13629609

    申请日：2012-09-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ming-Shun Hsu ,  Ke-Feng Lin ,  Chih-Chung Wang

    IPC: H01L29/78

    CPC classification number: H01L29/78 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/7816

    Abstract: A HV MOS transistor device is provided. The HV MOS transistor device includes a substrate comprising at least an insulating region formed thereon, a gate positioned on the substrate and covering a portion of the insulating region, a drain region and a source region formed at respective sides of the gate in the substrate, and a first implant region formed under the insulating region. The substrate comprises a first conductivity type, the drain, the source, and the first implant region comprise a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

    Abstract translation: 提供HV MOS晶体管器件。 HV MOS晶体管器件包括至少包括形成在其上的绝缘区域的衬底，位于衬底上并覆盖绝缘区域的一部分的栅极，形成在衬底中的栅极的各个侧面处的漏极区域和源极区域， 以及形成在所述绝缘区域下方的第一注入区域。 衬底包括第一导电类型，漏极，源极和第一注入区域包括第二导电类型，并且第一导电类型和第二导电类型彼此互补。

    Semiconductor device
    16.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11791386B2

    公开(公告)日：2023-10-17

    申请号：US17895054

    申请日：2022-08-24

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yi-Chieh Wang ,  Po-Chun Lai ,  Ke-Feng Lin ,  Chen-An Kuo ,  Ze-Wei Jhou

    IPC: H01L29/76 ,  H01L31/062 ,  H01L29/94 ,  H01L29/40 ,  H01L27/088 ,  H01L29/78

    CPC classification number: H01L29/404 ,  H01L27/088 ,  H01L29/7816

    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

    METHOD FOR FABRICATING TRANSISTOR STRUCTURE
    17.
    发明申请
    METHOD FOR FABRICATING TRANSISTOR STRUCTURE 有权

    公开(公告)号：US20220328685A1

    公开(公告)日：2022-10-13

    申请号：US17852371

    申请日：2022-06-29

    Applicant: United Microelectronics Corp.

    Inventor： Tseng Hsun Liu ,  Min-Hsuan Tsai ,  Ke-Feng Lin ,  Ming-Yen Liu ,  Wen-Chung Chang ,  Cherng-En Sun

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423

    Abstract: A method for fabricating a transistor includes providing a substrate, having a gate region and a first trench in the substate at a first side of the gate region; forming a first gate insulating layer, disposed on a first portion of the gate region, opposite to the first trench; forming a second gate insulating layer, disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer; forming a gate layer, disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench; forming a first doped region in the substrate at least under the first trench; and forming a second doped region in the substrate at a second side of the gate region.

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