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公开(公告)号：US09443587B1
公开(公告)日：2016-09-13
申请号：US14804354
申请日：2015-07-21
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Meng-Hung Lin , Ping-Kun Wang , Shao-Ching Liao , Chuan-Sheng Chou
CPC classification number: G11C13/0069 , G11C13/0064 , G11C2013/0066 , G11C2013/0073 , G11C2013/0076 , G11C2013/0078 , G11C2013/0092
Abstract: A resistive memory apparatus and a writing method thereof are provided. In the method, logic data is received, and a corresponding resistive memory cell is selected. A logic level of the logic data is determined. When the logic data is in a first logic level, where a first reading current of the corresponding resistive memory cell is greater than a first reference current, a set pulse and a reset pulse are provided to the resistive memory cell during a writing period. When the logic data is in a second logic level, where a second reading current of the resistive memory cell is smaller than a second reference current, the reset pulse is provided to the resistive memory cell during the writing period. Polarities of the reset pulse and the set pulse are opposite.
Abstract translation: 提供了一种电阻式存储装置及其写入方法。 在该方法中，接收逻辑数据，并且选择相应的电阻性存储单元。 确定逻辑数据的逻辑电平。 当逻辑数据处于第一逻辑电平（其中对应的电阻性存储单元的第一读取电流大于第一参考电流）时，在写入周期期间将设置脉冲和复位脉冲提供给电阻存储器单元。 当逻辑数据处于第二逻辑电平时，其中电阻存储单元的第二读取电流小于第二参考电流，在写入周期期间将复位脉冲提供给电阻存储单元。 复位脉冲和设定脉冲的极性相反。
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公开(公告)号：US20160055906A1
公开(公告)日：2016-02-25
申请号：US14463625
申请日：2014-08-19
Applicant: Winbond Electronics Corp.
Inventor： Chia-Hua Ho , Shao-Ching Liao , Ping-Kun Wang , Meng-Hung Lin
IPC: G11C13/00
Abstract: An operation method of a resistive random access memory (RRAM) cell is provided, wherein the RRAM cell includes a variable impedance element and a switch element connected in series. The operation method includes the following steps. When the switch element is turned-on, a writing signal is provided to the variable impedance element to set an impedance of the variable impedance element. In a first period, the writing signal is set to a first writing voltage level to transmit a first electrical energy to the variable impedance element. In a second period, a second electrical energy is transmitted to the variable impedance element by the writing signal. The second period is subsequent to the first period, the first electrical energy and the second electrical energy are greater than zero, and the second electrical energy is smaller than the first electrical energy.
Abstract translation: 提供了一种电阻随机存取存储器（RRAM）单元的操作方法，其中RRAM单元包括串联连接的可变阻抗元件和开关元件。 操作方法包括以下步骤。 当开关元件导通时，向可变阻抗元件提供写入信号以设置可变阻抗元件的阻抗。 在第一时段中，将写入信号设置为第一写入电压电平以向可变阻抗元件发送第一电能。 在第二时段中，通过写入信号将第二电能传输到可变阻抗元件。 第二时期是在第一时段之后，第一电能和第二电能大于零，第二电能小于第一电能。
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公开(公告)号：US12190980B2
公开(公告)日：2025-01-07
申请号：US18171666
申请日：2023-02-21
Applicant: Winbond Electronics Corp.
Inventor： Shao-Ching Liao , Chien-Min Wu , Kuang-Chih Hsieh
IPC: G11C29/50
Abstract: A semiconductor memory apparatus and a testing method thereof are provided. The semiconductor memory apparatus includes a memory chip and a memory controller. The memory controller is configured to detect an initial test voltage of a target memory cell corresponding to a tailing bit in a main array of the memory chip. After the memory chip is idle for a first time, the memory controller detects a first test voltage of the target memory cell and compares it with a current comparison voltage to determine whether a first stage test is passed. In a case of passing the first stage test, after the memory chip is idle for a second time, the memory controller detects a second test voltage of the target memory cell and compares it with the current comparison voltage to determine whether a second stage test is passed. The comparison voltage is dynamically updated in response to the time the memory chip is idle.
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公开(公告)号：US11620500B2
公开(公告)日：2023-04-04
申请号：US15868392
申请日：2018-01-11
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Shao-Ching Liao , Chih-Cheng Fu , Ming-Che Lin , Yu-Ting Chen , Seow-Fong (Dennis) Lim
Abstract: A synapse system is provided which includes three transistors and a resistance-switching element arranged between two neurons. The resistance-switching element has a resistance value and it is arranged between two neurons. A first transistor is connected between the resistance-switching element and one of the neurons. A second transistor and a third transistor are arranged between the two neurons, and are connected in series which interconnects with the gate of the first transistor. A first input signal is transmitted from one of the neurons to the other neuron through the first transistor. A second input signal is transmitted from one of the neurons to the other neuron through the second transistor and the third transistor. The resistance value of the resistance-switching element is changed based on the time difference between the first input signal and the second input signal.
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公开(公告)号：US11520526B2
公开(公告)日：2022-12-06
申请号：US17337003
申请日：2021-06-02
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Shao-Ching Liao , Chien-Min Wu , Chia Hua Ho , Frederick Chen , He-Hsuan Chao , Seow-Fong Lim
Abstract: A write method for a resistive memory including a storage array, a control circuit and an access circuit is provided. The control circuit receives an external command to activate the access circuit to access the storage array. The write method includes determining whether the external command is ready to perform a write operation for the storage array; generating a first operation voltage group to the access circuit when the external command does not perform the write operation for the storage array; reading a count value of a block that corresponds to a write address when the external command performs the write operation for the storage array, wherein the count value indicates the number of times that the block corresponding to the write address performs the write operation; and generating a second operation voltage group to the access circuit according to the count value of the block.
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Patent Agency Ranking
公开(公告)号：US20190221260A1
公开(公告)日：2019-07-18
申请号：US16181372
申请日：2018-11-06
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Shao-Ching Liao , Yu-Ting Chen , Ming-Che Lin , Chien-Min Wu , Chia-Hua Ho
IPC: G11C13/00
CPC classification number: G11C13/0038 , G11C13/0004 , G11C13/004 , G11C13/0064 , G11C2013/0045
Abstract: A power on reset method for a resistive memory storage device is provided and includes performing a forming procedure on a memory cell of the resistive memory storage device. The forming procedure includes applying at least one forming voltage and at least one reset voltage to the memory cell. The forming procedure further includes a thermal step. The step of applying at least one reset voltage to the memory cell may be preformed before or after the thermal step. After one forming voltage is applied, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. After the thermal step, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. In addition, after one reset voltage is applied, if the memory cell passes verification, the next reset voltage is not applied to the memory cell.
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17.发明申请公开(公告)号：US20180366197A1
公开(公告)日：2018-12-20
申请号：US15997717
申请日：2018-06-05
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Shao-Ching Liao , Ming-Che Lin , Min-Chih Wei , Chuan-Sheng Chou
IPC: G11C13/00
CPC classification number: G11C13/0097 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/52 , H01L45/1233 , H01L45/1253 , H01L45/143 , H01L45/146 , H01L45/147
Abstract: A resistive memory and a resistance window recovery method for a resistive memory cell thereof are provided. During a first period, an over reset voltage difference is applied between a top electrode and a bottom electrode of the resistive memory cell, wherein the over reset voltage difference falls in a reset complementary switching (reset-CS) voltage range of the resistive memory cell. During a second period, a set voltage difference is applied between the top electrode and the bottom electrode of the resistive memory cell to increase a compliance current of the resistive memory cell. During a third period, a reset operation is performed on the resistive memory cell.
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公开(公告)号：US20170117038A1
公开(公告)日：2017-04-27
申请号：US14918574
申请日：2015-10-21
Applicant: Winbond Electronics Corp.
Inventor： Shao-Ching Liao , Ping-Kun Wang , Frederick Chen
IPC: G11C13/00
CPC classification number: G11C11/00 , G11C5/147 , G11C11/5642 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , H01L27/2409 , H01L45/00
Abstract: An operating method for a resistive memory cell and a resistive memory are provided. The operating method for the resistive memory cell includes following steps. A forming operation for the resistive memory cell is performed. Whether the resistive memory cell is in a first state is determined, wherein the first state is corresponding to a first operation. When the resistive memory cell is not in the first state, a complementary switching operation regarding a second operation for the resistive memory cell is performed, so that the resistive memory cell generates a complementary switching phenomenon regarding the second operation. Thus, the resistive memory cell which cannot retain data by normal forming operation can effectively obtain the data retention capability by the complementary switching phenomenon.
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公开(公告)号：US09496036B1
公开(公告)日：2016-11-15
申请号：US14953447
申请日：2015-11-30
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Shao-Ching Liao , Pei-Hsiang Liao
CPC classification number: G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2013/009 , G11C2013/0092 , G11C2213/79 , G11C2213/82
Abstract: A writing method for a resistive memory cell and a resistive memory are provided. The writing method includes following steps. A reference voltage is provided to a bit line of the resistive memory cell. A first voltage is provided to a word line of the resistive memory cell, and a second voltage is provided to a source line of the resistive memory cell, wherein the first voltage is not increased while the second voltage is progressively increased. Thus, when the writing method for the resistive memory cell is performed, the voltage of the word line is not increased while the voltage of the source line is progressively increased, so as to expand voltage window for reset operation. And, the chance for occurring the complementary switching manifestation of the resistive memory cell due to excessive input voltages is reduced.
Abstract translation: 提供了一种用于电阻式存储单元和电阻式存储器的写入方法。 写作方法包括以下步骤。 参考电压被提供给电阻存储单元的位线。 第一电压被提供给电阻存储单元的字线，并且第二电压被提供给电阻存储单元的源极线，其中第一电压不增加，而第二电压逐渐增加。 因此，当执行电阻性存储单元的写入方法时，在线源的电压逐渐增加的同时，字线的电压不增加，从而扩大用于复位操作的电压窗口。 并且，由于过大的输入电压而发生电阻式存储单元的互补切换表现的机会降低。
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公开(公告)号：US11538525B2
公开(公告)日：2022-12-27
申请号：US17495778
申请日：2021-10-06
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Ming-Che Lin , Yu-Ting Chen , Chang-Tsung Pai , Shao-Ching Liao , Chi-Ching Liu
Abstract: Provided is a resetting method of a resistive random access memory (RRAM) including the following steps. A first resetting operation and a first verifying operation on the at least one resistive memory cell are performed. Whether to perform a second resetting operation according to a verifying result of the first verifying operation is determined. A second verifying operation is performed after the second resetting operation is determined to be performed and is finished. To determine whether to perform a healing resetting operation according to a verifying result of the second verifying operation, which comprises: performing the healing resetting operation when a verifying current of the second verifying operation is greater than a predetermined current, wherein a resetting voltage of the healing resetting operation is greater than a resetting voltage of the second resetting operation.
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