公开(公告)号：US20140332969A1

公开(公告)日：2014-11-13

申请号：US14339355

申请日：2014-07-23

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Shu-Ming CHANG ,  Yu-Lung HUANG ,  Chao-Yen LIN ,  Wei-Luen SUEN ,  Chien-Hui CHEN ,  Chi-Chang LIAO

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L21/561 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/10523 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3701 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess extends from a first bottom of the first recess toward the lower surface. The first and second recesses further laterally extend along a side of the upper surface, and a length of the first recess extending along the side is greater than that of the second recess extending along the side. A redistribution layer is electrically connected to the signal pad region and extends into the second recess. A method for forming the chip package is also provided.

Abstract translation: 提供了包括具有上表面，下表面和侧壁的芯片的芯片封装。 芯片包括与上表面相邻的信号焊盘区域。 第一凹部沿着侧壁从上表面向下表面延伸。 至少一个第二凹部从第一凹部的第一底部向下表面延伸。 第一和第二凹部沿着上表面的侧面进一步横向延伸，并且沿着侧面延伸的第一凹部的长度大于沿着侧面延伸的第二凹部的长度。 再分配层电连接到信号焊盘区域并延伸到第二凹槽中。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US20140203387A1

公开(公告)日：2014-07-24

申请号：US14157379

申请日：2014-01-16

Applicant: XINTEC INC.

Inventor： Wei-Luen SUEN ,  Shu-Ming CHANG ,  Yu-Lung HUANG ,  Yen-Shih HO ,  Tsang-Yu LIU

IPC: H01L31/02

CPC classification number: H01L31/02005 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/525 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/11472 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/00014 ,  H01L2224/0231 ,  H01L2224/11

Abstract: Disclosed herein is a semiconductor chip package, which includes a semiconductor chip, a plurality of vias, an isolation layer, a redistribution layer, and a packaging layer. The vias extend from the lower surface to the upper surface of the semiconductor chip. The vias include at least one first via and at least one second via. The isolation layer also extends from the lower surface to the upper surface of the semiconductor chip, and part of the isolation layer is disposed in the vias. The sidewall of the first via is totally covered by the isolation layer while the sidewall of the second via is partially covered by the isolation layer. The redistribution layer is disposed below the isolation layer and fills the plurality of vias, and the packaging layer is disposed below the isolation layer.

Abstract translation: 这里公开了一种半导体芯片封装，其包括半导体芯片，多个通孔，隔离层，再分布层和封装层。 通孔从半导体芯片的下表面延伸到上表面。 通孔包括至少一个第一通孔和至少一个第二通孔。 隔离层也从半导体芯片的下表面延伸到上表面，并且隔离层的一部分设置在通孔中。 第一通孔的侧壁完全被隔离层覆盖，而第二通孔的侧壁被隔离层部分地覆盖。 再分配层设置在隔离层下方并填充多个通孔，并且包装层设置在隔离层下方。

公开(公告)号：US20250054849A1

公开(公告)日：2025-02-13

申请号：US18779105

申请日：2024-07-22

Applicant: Xintec Inc.

Inventor： Wei-Luen SUEN ,  Po-Jung CHEN ,  Chia-Ming CHENG ,  Po-Shen LIN ,  Jiun-Yen LAI ,  Tsang-Yu LIU ,  Shu-Ming CHANG

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/15 ,  H01L23/528

Abstract: A chip package is provided. The chip package includes a device substrate, a first redistribution layer (RDL), a carrier base, and at least one conductive connection structure. The device substrate has at least one first through-via opening extending from the backside surface of the device substrate to the active surface of the device substrate. The first RDL is disposed on the backside surface of the device substrate and extends in the first through-via opening. The carrier base carries the device substrate, and has a first surface facing the backside surface of the device substrate and a second surface opposite the first surface. The conductive connection structure is disposed on the second surface of the carrier base and is electrically connected to the first RDL.

公开(公告)号：US20220069454A1

公开(公告)日：2022-03-03

申请号：US17407068

申请日：2021-08-19

Applicant: XINTEC INC.

Inventor： Jiun-Yen LAI ,  Ming-Chung CHUNG ,  Wei-Luen SUEN

IPC: H01Q1/38 ,  H01Q1/52

Abstract: An antenna device includes a first substrate, a second substrate, an antenna layer, and a redistribution layer. The first substrate has a first surface, a second surface opposite to the first surface, and an inclined sidewall adjoining the first and second surfaces. The second substrate is below the first substrate. The first surface of the first substrate faces toward the second substrate. The antenna layer is located on the first surface of the first substrate. The redistribution layer extends from the second surface of the first substrate to the second substrate along the inclined sidewall of the first substrate, and the redistribution layer has a first section in contact with an end of the antenna layer.

公开(公告)号：US20160355393A1

公开(公告)日：2016-12-08

申请号：US15171971

申请日：2016-06-02

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Wei-Luen SUEN ,  Po-Han LEE

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0081 ,  B81B7/0077 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3677 ,  H01L23/481 ,  H01L2224/11

Abstract: A chip package includes a chip having an upper surface and a lower surface. A sensing element is disposed on the upper surface of the chip, and a thermal dissipation layer is disposed below the lower surface of the chip. A plurality of thermal dissipation external connections are disposed below the thermal dissipation layer and in contact with the thermal dissipation layer.

Abstract translation: 芯片封装包括具有上表面和下表面的芯片。 感测元件设置在芯片的上表面上，并且散热层设置在芯片的下表面下方。 多个散热外部连接设置在散热层下方并与散热层接触。

公开(公告)号：US20140332968A1

公开(公告)日：2014-11-13

申请号：US14339323

申请日：2014-07-23

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Shu-Ming CHANG ,  Yu-Lung HUANG ,  Chao-Yen LIN ,  Wei-Luen SUEN ,  Chien-Hui CHEN

IPC: H01L23/498

CPC classification number: H01L23/49805 ,  G06K9/00006 ,  G06K9/00053 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal pad region adjacent to the upper surface. A shallow recess structure is located outside of the signal pad region and extends from the upper surface toward the lower surface along the sidewall. The shallow recess structure has at least a first recess and a second recess under the first recess. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A first end of a wire is located in the shallow recess structure and is electrically connected to the redistribution layer. A second end of the wire is used for external electrical connection. A method for forming the chip package is also provided.

Abstract translation: 提供芯片封装。 芯片封装包括具有上表面，下表面和侧壁的芯片。 芯片包括感测区域或器件区域以及与上表面相邻的信号焊盘区域。 浅凹陷结构位于信号垫区域的外侧，并且沿着侧壁从上表面向下表面延伸。 浅凹部结构在第一凹部下方具有至少第一凹部和第二凹部。 再分配层电连接到信号焊盘区域并延伸到浅凹陷结构中。 电线的第一端位于浅凹陷结构中，并且电连接到再分配层。 电线的第二端用于外部电气连接。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US20130307125A1

公开(公告)日：2013-11-21

申请号：US13950101

申请日：2013-07-24

Applicant: XINTEC INC.

Inventor： Yu-Lung HUANG ,  Chao-Yen LIN ,  Wei-Luen SUEN ,  Chien-Hui CHEN

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49805 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/16 ,  H01L24/48 ,  H01L24/95 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having an upper surface and a lower surface; a device region or sensing region defined in the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; at least two recesses extending from the upper surface towards the lower surface of the semiconductor substrate, wherein sidewalls and bottoms of the recesses together form a sidewall of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to the sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有上表面和下表面的半导体衬底; 限定在所述半导体衬底中的器件区域或感测区域; 导电焊盘，位于所述半导体衬底的上表面上; 至少两个从所述半导体衬底的上表面向下表面延伸的凹槽，其中所述凹槽的侧壁和底部一起形成所述半导体衬底的侧壁; 导电层，电连接到导电焊盘并从半导体衬底的上表面延伸至半导体衬底的侧壁; 以及位于导电层和半导体衬底之间的绝缘层。

公开(公告)号：US20240351865A1

公开(公告)日：2024-10-24

申请号：US18622059

申请日：2024-03-29

Applicant: Xintec Inc.

Inventor： Jiun-Yen LAI ,  Wei-Luen SUEN ,  Ming-Chung CHUNG ,  Chih-Wei LIU

IPC: B81C1/00

CPC classification number: B81C1/00825 ,  B81C2201/013 ,  B81C2201/0143 ,  B81C2201/0146 ,  B81C2201/0159

Abstract: A manufacturing method of a micro electro mechanical system (MEMS) device includes forming a buffer protection layer on a semiconductor structure, wherein the semiconductor structure includes a wafer, a MEMS membrane, and an isolation layer between the wafer and the MEMS membrane, and the buffer protection layer is located in a slit of the MEMS membrane and on a surface of the MEMS membrane facing away from the isolation layer; etching the wafer to form a cavity such that a portion of the isolation layer is exposed though the cavity; etching the portion of the isolation layer; and removing the buffer protection layer.

公开(公告)号：US20210210538A1

公开(公告)日：2021-07-08

申请号：US17133636

申请日：2020-12-24

Applicant: XINTEC INC.

Inventor： Jiun-Yen LAI ,  Wei-Luen SUEN ,  Hsing-Lung SHEN ,  Yu-Ting HUANG

IPC: H01L27/146

Abstract: A chip package is provided. The chip package includes a first substrate and a second substrate disposed over the first substrate. The first substrate and the second substrate have a lower surface and an upper surface, and the second substrate includes a first recess region surrounding the second substrate. The first recess region has a tapered sidewall and a bottom surface that is between the lower and upper surfaces of the second substrate. The chip package also includes at least one conductive pad disposed on the upper surface of the second substrate and a redistribution layer (RDL) correspondingly disposed on the conductive pad. The RDL is extended from the conductive pad onto the bottom surface of the first recess region along the tapered sidewall of the first recess region. A method of forming a chip package is also provided.

公开(公告)号：US20210104455A1

公开(公告)日：2021-04-08

申请号：US17037151

申请日：2020-09-29

Applicant: XINTEC INC.

Inventor： Wei-Luen SUEN ,  Jiun-Yen LAI ,  Hsing-Lung SHEN ,  Tsang-Yu LIU

IPC: H01L23/498 ,  H01L21/48

Abstract: A chip package includes a lower substrate, a first silicon nitride substrate, a bonding layer, an upper substrate, a first functional layer, a transparent conductive layer, an isolation layer, and a first conductive pad. The supporting layer is located between the lower substrate and the first silicon nitride substrate, and is made of a material including Benzocyclobutene (BCB). The upper substrate is located on the first silicon nitride substrate. The first functional layer is located between the upper substrate and the first silicon nitride substrate. The transparent conductive layer is located on the upper substrate. The isolation layer covers the upper substrate and the transparent conductive layer. The first conductive pad is located in the isolation layer and in electrical contact with the transparent conductive layer.