公开(公告)号：US20170125077A1

公开(公告)日：2017-05-04

申请号：US15258672

申请日：2016-09-07

申请人： Samsung Electronics Co., Ltd.

发明人： Hun-dae Choi ,  Young-kwon Jo

IPC分类号： G11C7/22 ,  H03K5/14 ,  H03L7/081

CPC分类号： G11C7/222 ,  G11C7/1066 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/023 ,  H03K5/14 ,  H03K2005/00019 ,  H03L7/0812 ,  H03L7/0816

摘要： Provided is a delay-locked loop circuit for providing a delay-locked clock signal to a data output buffer, the delay-locked loop circuit including: a first delay-locked-mode-based selector configured to select, as a first selected clock signal, one of a first divided clock signal, which is obtained by dividing a reference clock signal by N, and the reference clock signal; and a delay-locked mode controller configured to determine a delay-locked mode on the basis of a command received from the outside and to control the first delay-locked-mode-based selector according to the delay-locked mode. The delay-locked clock signal is generated by comparing a phase of a feedback clock signal generated from the first selected clock signal with a phase of the reference clock signal.

公开(公告)号：US20170063359A1

公开(公告)日：2017-03-02

申请号：US14842591

申请日：2015-09-01

申请人： FUJITSU LIMITED

发明人： Nikola NEDOVIC

IPC分类号： H03K5/1534 ,  H03L7/081 ,  H03L7/091 ,  H03K3/037

CPC分类号： H03K5/1534 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/091

摘要： A phase detection circuit includes a first sample circuit, a second sample circuit, and a third sample circuit. The first sample circuit may be configured to sample a first signal based on a first phase of a second signal to generate a first sample of the first signal and to output the first sample. The second sample circuit may be configured to sample the first signal based on a second phase of the second signal to generate a second sample of the first signal and to output second sample. The third sample circuit coupled to the first sample circuit and to the second sample circuit. The third sample circuit may be configured to sample the first sample based on a change of the second sample to generate a third sample and to output the third sample.

摘要翻译： 相位检测电路包括第一采样电路，第二采样电路和第三采样电路。 第一采样电路可以被配置为基于第二信号的第一相位采样第一信号，以产生第一信号的第一采样并输出第一采样。 第二采样电路可以被配置为基于第二信号的第二相位对第一信号进行采样，以产生第一信号的第二采样并输出第二采样。 第三采样电路耦合到第一采样电路和第二采样电路。 第三采样电路可以被配置为基于第二采样的变化对第一采样进行采样，以产生第三采样并输出第三采样。

公开(公告)号：US09577649B1

公开(公告)日：2017-02-21

申请号：US15069082

申请日：2016-03-14

申请人： Altera Corporation

发明人： Boon Pin Liong ,  Chooi Pei Lim

IPC分类号： H03L7/00 ,  H03L7/08 ,  H03L7/091 ,  H03L7/095 ,  H03K5/1534

CPC分类号： H03L7/0802 ,  G06F1/10 ,  H03K5/135 ,  H03K5/1534 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/0816

摘要： Integrated circuits with clock distribution circuitry are provided. The clock distribution circuitry may include a clock source, a clock distribution network, a frequency encoder placed at the output of the clock source, and one or more frequency decoders placed at the destinations of the clock distribution network. The frequency encoder can be used to obtain calibrated delay settings proportional to a reference clock generated by the clock source. Each frequency decoder can be placed in a closed loop configuration and can use the calibrated delay settings to locally self-generate a recovered clock at the destination during a locked state. During the locked state, clock buffers in the clock distribution network can be powered down to save power.

摘要翻译： 提供了具有时钟分配电路的集成电路。 时钟分配电路可以包括时钟源，时钟分配网络，放置在时钟源的输出端的频率编码器，以及放置在时钟分配网络的目的地的一个或多个频率解码器。 频率编码器可用于获得与时钟源产生的参考时钟成比例的校准延迟设置。 可以将每个频率解码器置于闭环配置中，并且可以使用校准的延迟设置在锁定状态期间在目的地本地自生产恢复的时钟。 在锁定状态下，时钟分配网络中的时钟缓冲器可以掉电以节省电力。

公开(公告)号：US09564907B2

公开(公告)日：2017-02-07

申请号：US14810900

申请日：2015-07-28

申请人： SK hynix Inc. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

发明人： Joo-Hyung Chae ,  Suhwan Kim ,  Deog-Kyoon Jeong

IPC分类号： H03L7/06 ,  H03L7/07 ,  H03L7/085 ,  H03L7/08 ,  H03L7/081 ,  H03L7/087

CPC分类号： H03L7/07 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/085 ,  H03L7/087

摘要： A multi-channel delay locked loop includes a global delay locked loop and a plurality of local delay locked loops. The global delay locked loop is configured to lock an input clock signal and output a global delay control signal corresponding to a delay amount of the input clock signal during a locking operation. Each of the plurality of local delay locked loops is configured to output a channel clock signal by locking the input clock signal, and initialize the delay amount of the input clock signal according to the global delay control signal.

摘要翻译： 多通道延迟锁定环路包括全局延迟锁定环路和多个本地延迟锁定环路。 全局延迟锁定环被配置为在锁定操作期间锁定输入时钟信号并输出​​对应于输入时钟信号的延迟量的全局延迟控制信号。 多个本地延迟锁定环中的每一个被配置为通过锁定输入时钟信号来输出通道时钟信号，并且根据全局延迟控制信号初始化输入时钟信号的延迟量。

公开(公告)号：US09264054B1

公开(公告)日：2016-02-16

申请号：US14607856

申请日：2015-01-28

申请人： Marvell International Ltd.

发明人： Ross Swanson

IPC分类号： H03L7/06 ,  H03L7/095

CPC分类号： H03L7/095 ,  H03L7/0814 ,  H03L7/0816

摘要： An apparatus includes a lock detect circuit configured to receive a phase detect signal and generate a lock signal according to the phase detect signal. The phase detect signal is a single bit signal having a first value or a second value. A method includes receiving a phase detect signal using a lock detect circuit, and generating a lock signal according to the phase detect signal. The phase detect signal is a single bit signal having a first value or a second value.

摘要翻译： 一种装置，包括：锁定检测电路，被配置为接收相位检测信号，并根据相位检测信号产生锁定信号。 相位检测信号是具有第一值或第二值的单位信号。 一种方法包括使用锁定检测电路接收相位检测信号，并根据相位检测信号产生锁定信号。 相位检测信号是具有第一值或第二值的单位信号。

公开(公告)号：US20160043860A1

公开(公告)日：2016-02-11

申请号：US14644216

申请日：2015-03-11

申请人： Novatek Microelectronics Corp.

发明人： Chao-Kai Tu ,  Rong-Sing Chu

IPC分类号： H04L7/00 ,  H03L7/07 ,  H03L7/08 ,  H03L7/089 ,  H03L7/093 ,  H03L7/087 ,  H03L7/091

CPC分类号： H03L7/0807 ,  H03L7/0816 ,  H03L7/087 ,  H04L7/0037 ,  H04L7/0337

摘要： A clock and data recovery apparatus which includes a voltage controlled delay line (VCDL), a phase detector (PD) and a control voltage generating circuit is provided. The VCDL generates a plurality of clock signals with different phases according to a reference clock signal and a control voltage. The PD detects the phase relationship between a first input signal and a second input signal, and produces a detection result. A data signal or one of the clock signals is used as the first input signal, and one or more of the clock signals is/are used as the second input signal. The control voltage generating circuit generates the control voltage to the VCDL according to the detection result of the PD.

摘要翻译： 提供了包括电压控制延迟线（VCDL），相位检测器（PD）和控制电压产生电路的时钟和数据恢复装置。 VCDL根据参考时钟信号和控制电压产生具有不同相位的多个时钟信号。 PD检测第一输入信号和第二输入信号之间的相位关系，并产生检测结果。 使用数据信号或时钟信号之一作为第一输入信号，并且使用一个或多个时钟信号作为第二输入信号。 控制电压产生电路根据PD的检测结果生成对VCDL的控制电压。

公开(公告)号：US20160028537A1

公开(公告)日：2016-01-28

申请号：US14810087

申请日：2015-07-27

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Mustafa Ulvi ERDOGAN ,  Sridhar RAMASWAMY

IPC分类号： H04L7/033

CPC分类号： H04L7/033 ,  H03L7/0816 ,  H04L7/0337 ,  H04L25/00

摘要： A phase detector and retimer circuit that includes a retimer circuit, a phase shift circuit coupled to the retimer circuit, and an error signal generation circuit coupled to the retimer circuit and the phase shift circuit. The retimer circuit is configured to receive a data signal and generate a first retimed data signal based on a first phase of a clock signal and a second retimed data signal based on a second phase of the clock signal. The phase shift circuit is configured to receive the data signal and phase shift the data signal to generate first, second, third, and fourth phase shifted data signals. The error signal generation circuit is configured to generate a first error signal and a second error signal based on the first and second retimed data signals and the first, second, third, and fourth phase shifted data signals.

摘要翻译： 包括重定时器电路，耦合到重定时器电路的相移电路和耦合到重定时器电路和相移电路的误差信号产生电路的相位检测器和重新定时器电路。 重新定时器电路被配置为接收数据信号，并且基于时钟信号的第一相位和基于时钟信号的第二相位的第二重定时数据信号来生成第一重新定时数据信号。 相移电路被配置为接收数据信号并且相移数据信号以产生第一，第二，第三和第四相移数据信号。 误差信号生成电路被配置为基于第一和第二重定时数据信号以及第一，第二，第三和第四相移数据信号产生第一误差信号和第二误差信号。

公开(公告)号：US20150372685A1

公开(公告)日：2015-12-24

申请号：US14745118

申请日：2015-06-19

申请人： Micron Technology, Inc.

发明人： KATSUHIRO KITAGAWA

IPC分类号： H03L7/099

CPC分类号： H03L7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  H03K3/0315 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0997 ,  H03L7/0998

摘要： According to the present invention, a ring oscillator coupled to an output node operable to output a clock signal including a first logic level generated by a first odd number of delay circuits, and a second logic level different from the first logic level generated by a second odd number of delay circuits different from the first odd number of delay circuits.

摘要翻译： 根据本发明，耦合到输出节点的环形振荡器可操作以输出包括由第一奇数个延迟电路产生的第一逻辑电平的时钟信号和与第二逻辑电平产生的第二逻辑电平不同的第二逻辑电平 与第一奇数个延迟电路不同的奇数个延迟电路。

公开(公告)号：US09160350B2

公开(公告)日：2015-10-13

申请号：US13676945

申请日：2012-11-14

申请人： Rambus Inc.

发明人： Jared L. Zerbe ,  Masum Hossain ,  Pak S. Chau

IPC分类号： H03L7/06 ,  H03L7/091 ,  G11C8/18 ,  H03K5/156 ,  H03L7/08 ,  H03L7/081 ,  H03L7/083 ,  H03L7/099 ,  H03L7/10 ,  G11C7/10 ,  G11C7/22 ,  G11C7/04

CPC分类号： H03L7/091 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/222 ,  G11C8/18 ,  H03K5/1565 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/083 ,  H03L7/0995 ,  H03L7/104

摘要： Embodiments of an integrated circuit (IC) comprising a delay-locked loop (DLL) are described. Some embodiments include first circuitry to generate a first clock signal by delaying an input clock signal by a first delay, second circuitry to determine a code based on the input clock signal and the first clock signal, and third circuitry to produce an output clock signal based on the input clock signal and the code. In some embodiments, the power consumption of the DLL circuitry is reduced by powering down at least some parts of the DLL circuitry for most of the time. In some embodiments, the clock signal that is used to clock the command-and-address circuitry of a memory device is used to clock the on-die-termination latency counter circuitry.

摘要翻译： 描述了包括延迟锁定环（DLL）的集成电路（IC）的实施例。 一些实施例包括通过将输入时钟信号延迟第一延迟来产生第一时钟信号的第一电路，基于输入时钟信号和第一时钟信号确定代码的第二电路，以及基于输出时钟信号的第三电路 对输入时钟信号和代码。 在一些实施例中，通过在大多数时间内断电DLL电路的至少一些部分来降低DLL电路的功耗。 在一些实施例中，用于对存储器件的命令和地址电路进行时钟的时钟信号用于对片上终端等待时间计数器电路进行时钟。

公开(公告)号：US09160349B2

公开(公告)日：2015-10-13

申请号：US12548883

申请日：2009-08-27

申请人： Yantao Ma

发明人： Yantao Ma

IPC分类号： G06F1/04 ,  H03L7/081 ,  G11C7/22 ,  G11C29/02 ,  G11C5/02

CPC分类号： H03L7/0812 ,  G11C5/02 ,  G11C7/222 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2924/15311 ,  H01L2924/3011 ,  H03L7/0814 ,  H03L7/0816 ,  H01L2924/00

摘要： Embodiments are described that compensate for a difference in a characteristic (e.g., of performance or operation) of a semiconductor device that is a function of the location of a die in a device. In one embodiment, a clock circuit may generate a clock signal having a timing that varies with the location of a die so that signals are coupled from the die to a substrate at the same time despite differences in the signal propagation time between the substrate and the various die. In other embodiments, for example, differences in the termination impedance or driver drive-strength resulting from differences in the location of a die in a stack may be compensated for. Other embodiments are also disclosed.

摘要翻译： 描述了补偿作为设备中的管芯位置的函数的半导体器件的特性（例如，性能或操作）的差异的实施例。 在一个实施例中，时钟电路可以产生具有随芯片位置变化的定时的时钟信号，使得尽管信号传播时间在衬底和衬底之间存在差异，但是信号同时从管芯耦合到衬底 各种死亡 在其他实施例中，例如，可以补偿由堆叠中的管芯的位置的差异导致的终止阻抗或驱动器驱动强度的差异。 还公开了其他实施例。