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101 条记录 (耗时 0.014 秒)

    High performance bipolar transistors fabricated by post emitter base implantation process
    11.
    发明授权
    High performance bipolar transistors fabricated by post emitter base implantation process 失效
    通过后发射极基极注入工艺制造的高性能双极晶体管

    公开(公告)号：US4242791A

    公开(公告)日：1981-01-06

    申请号：US77699

    申请日：1979-09-21

    申请人： Cheng T. Horng ,  Harold V. Lillja ,  David K. Seto

    发明人： Cheng T. Horng ,  Harold V. Lillja ,  David K. Seto

    IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/266 ,  H01L21/316 ,  H01L21/331 ,  H01L21/76 ,  H01L29/10 ,  B01J17/00

    CPC分类号： H01L29/1004 ,  H01L21/033 ,  H01L21/31687 ,  Y10S148/131

    摘要： Disclosed is a method for fabricating very high performance semiconductor devices, particularly bipolar-type transistors having a heavily doped inactive base and a lightly doped narrow active base formed by ion implantation. In order to prevent the high dose boron implantation, for an NPN transistor, from getting into the active base region, a self-aligned mask covering the emitter contact i.e., active base region, is required for inactive base implantation. The self-aligned mask is anodically oxidized aluminum pads. The device wafer metallized with blanket aluminum film is immersed in a dilute H.sub.2 SO.sub.4 solution electrolytic cell which selectively anodizes only the aluminum lands situated over the Si.sub.3 N.sub.4 /SiO.sub.2 defined device contact windows. The aluminum oxide formed by anodization process is porous but may be sealed and densified. The aluminum film that is not anodized is then selectively etched off using either chemical solution or sputter etching. Using the aluminum oxide formed over the contact windows to mask the active base region, a high dose boron implantation is made through the Si.sub.3 N.sub.4 /SiO.sub.2 layers to dope the external base region. After stripping the aluminum oxide from the emitter contact window, the emitter with a desired concentration profile and junction depth is subsequently formed. Formation of the active base is formed by a low dose boron implantation made with its concentration peak below the emitter. A relatively low temperature annealing, as for example, 900.degree. C., is used to fully activate the implanted boron and minimize the redistribution of the active base doping profile. The device thus formed will have a controllable narrow base width and doping profile.

    摘要翻译： 公开了一种用于制造非常高性能的半导体器件的方法，特别是具有重掺杂非活性碱和通过离子注入形成的轻掺杂窄活性碱的双极型晶体管。 为了防止对于NPN晶体管的高剂量硼注入进入有源基极区域，需要一个覆盖发射极接触的自对准掩模，即有源基极区域，用于无源基极植入。 自对准掩模是阳极氧化铝垫。 用橡皮布铝膜金属化的器件晶片浸入稀释的H 2 SO 4溶液电解池中，该电解池仅选择性地阳极氧化位于Si 3 N 4 / SiO 2界定的器件接触窗上方的铝焊盘。 通过阳极氧化法形成的氧化铝是多孔的，但可以被密封和致密化。 然后使用化学溶液或溅射蚀刻选择性地蚀刻掉未阳极氧化的铝膜。 使用形成在接触窗口上的氧化铝来掩蔽活性碱性区域，通过Si 3 N 4 / SiO 2层制备高剂量硼注入以掺杂外部碱性区域。 在从发射极接触窗口剥离氧化铝之后，随后形成具有所需浓度分布和结深度的发射极。 活性碱的形成是通过低浓度硼掺杂形成的，其浓度峰值低于发射极。 使用相对低温退火（例如900℃）来完全激活注入的硼并最小化活性碱掺杂分布的再分配。 如此形成的器件将具有可控的窄基极宽度和掺杂分布。

    Planar deep oxide isolation process utilizing resin glass and E-beam exposure
    12.
    发明授权
    Planar deep oxide isolation process utilizing resin glass and E-beam exposure 失效
    采用树脂玻璃和电子束曝光的平面深氧化物隔离工艺

    公开(公告)号：US4222792A

    公开(公告)日：1980-09-16

    申请号：US73593

    申请日：1979-09-10

    申请人： Reginald F. Lever ,  John L. Mauer, IV ,  Alwin E. Michel ,  Laura B. Rothman

    发明人： Reginald F. Lever ,  John L. Mauer, IV ,  Alwin E. Michel ,  Laura B. Rothman

    IPC分类号： H01L21/76 ,  H01L21/31 ,  H01L21/312 ,  H01L21/316 ,  H01L21/762 ,  H01L21/26

    CPC分类号： H01L21/316 ,  H01L21/3121 ,  H01L21/76229 ,  Y10S148/131

    摘要： A planar deep oxide isolation process for providing deep wide silicon dioxide filled trenches in the planar surface of a silicon semiconductor substrate, said process comprising the steps:(a) forming deep wide trenches in the planar surface of the silicon substrate;(b) forming a thin layer of silicon dioxide on the planar surface of the silicon substrate and the exposed silicon surfaces of said deep wide trenches;(c) applying resin glass (polysiloxane) to the planar surface of said semiconductor substrate and within said deep wide trenches;(d) spinning off at least a portion of the resin glass on the planar surface of the substrate;(e) baking the substrate at a low temperature;(f) exposing the resin glass contained within the deep wide trenches of substrate to the energy of an E-beam;(g) developing the resin glass contained on said substrate in a solvent;(h) heating said substrate in oxygen to convert said resin glass contained within said deep wide trenches to silicon dioxide;(i) depositing a layer of silicon dioxide to provide a planar silicon dioxide surface on the exposed the surface of said substrate; and(j) planarize exposed silicon dioxide surface to silicon of substrate.A planar deep oxide isolation process for providing deep wide silicon dioxide filled trenches in the planar surface of a silicon semiconductor substrate as recited in the preceding paragraph, wherein the following steps are performed in lieu of step i of claim 1, said steps comprising:(i-1) apply a second thin layer of resin glass; and(i-2) convert said resin glass to silicon dioxide.

    摘要翻译： 一种用于在硅半导体衬底的平面表面中提供深宽二氧化硅填充沟槽的平面深氧化物隔离工艺，所述方法包括以下步骤：（a）在硅衬底的平面表面中形成深宽沟槽; （b）在硅衬底的平面表面和所述深宽沟槽的暴露的硅表面上形成二氧化硅薄层; （c）将树脂玻璃（聚硅氧烷）施加到所述深宽沟槽的所述半导体衬底的平面上; （d）在所述基板的平面上剥离所述树脂玻璃的至少一部分; （e）在低温下烘烤该基材; （f）将包含在基底的深宽沟槽内的树脂玻璃暴露于电子束的能量; （g）在溶剂中显影所述基板上所含的树脂玻璃; （h）在氧气中加热所述衬底以将包含在所述深宽沟槽内的所述树脂玻璃转化为二氧化硅; （i）沉积二氧化硅层以在所述衬底的暴露的表面上提供平面二氧化硅表面; 和（j）将暴露的二氧化硅表面平坦化到衬底的硅。 一种用于在前述段落中提供的硅半导体衬底的平坦表面中提供深宽二氧化硅填充沟槽的平面深氧化物隔离工艺，其中执行以下步骤代替权利要求1的步骤i，所述步骤包括：（ i-1）涂一层树脂玻璃; 和（i-2）将所述树脂玻璃转化为二氧化硅。

    Dielectrically isolated semiconductor devices
    15.
    发明授权
    Dielectrically isolated semiconductor devices 失效
    绝缘半导体器件

    公开(公告)号：US3966577A

    公开(公告)日：1976-06-29

    申请号：US466722

    申请日：1974-05-03

    申请人： Arthur K. Hochberg

    发明人： Arthur K. Hochberg

    IPC分类号： H01L21/263 ,  H01L21/308 ,  H01L21/76 ,  H01L21/762 ,  C23C15/00 ,  H01L21/302 ,  H01L21/314

    CPC分类号： H01L21/76297 ,  H01L21/2633 ,  H01L21/308 ,  H01L21/76 ,  Y10S148/051 ,  Y10S148/131

    摘要： The invention is a method of fabricating dielectrically isolated semiconductor regions adapted for the construction of an integrated circuit on an epitaxial wafer wherein the epitaxial wafer has a first layer of monocrystalline n+ type silicon of a predetermined thickness and a second layer of epitaxially deposited n-type silicon which is substantially thinner than the first layer. A layer of silicon dioxide is grown on the back side of the first layer of the wafer and a layer of polycrystalline silicon is deposited onto the silicon dioxide layer. An aluminum oxide mask is formed defining a plurality of grooves around active semiconductor regions within the n-type silicon layer. The grooves are formed by a sputter etching process. Silicon dioxide is thermally grown within each of the grooves exposed by the sputter etching process to dielectrically isolate the active semiconductor regions after which semiconductor devices may be formed in each of the active semiconductor regions.

    摘要翻译： 本发明是一种制造适于在外延晶片上构建集成电路的介电隔离的半导体区域的方法，其中外延晶片具有预定厚度的第一层单晶n +型硅和第二层外延沉积的n型 基本上比第一层薄的硅。 在晶片的第一层的背面生长二氧化硅层，并且在二氧化硅层上沉积多晶硅层。 形成在n型硅层内限定有源半导体区周围的多个沟槽的氧化铝掩模。 通过溅射蚀刻工艺形成凹槽。 在通过溅射蚀刻工艺暴露的每个沟槽内热生长二氧化硅以介电地隔离有源半导体区域，其后可以在每个有源半导体区域中形成半导体器件。

    Method for manufacturing a semiconductor device with stabilization of a bipolar transistor and a schottky barrier diode
    16.
    发明授权
    Method for manufacturing a semiconductor device with stabilization of a bipolar transistor and a schottky barrier diode 失效
    用于制造具有双极晶体管和肖特基势垒二极管稳定的半导体器件的方法

    公开(公告)号：US5926705A

    公开(公告)日：1999-07-20

    申请号：US736037

    申请日：1996-10-21

    申请人： Takuo Nishida

    发明人： Takuo Nishida

    IPC分类号： H01L21/336 ,  H01L21/304 ,  H01L21/306 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/78

    CPC分类号： H01L21/8249 ,  H01L27/0635 ,  Y10S148/009 ,  Y10S148/051 ,  Y10S148/131 ,  Y10S148/139

    摘要： In a method for manufacturing an LDD-structured MOS transistor and a bipolar transistor, a gate insulating layer is formed on a MOS transistor region and a bipolar transistor region. Then, a gate electrode is formed on the MOS transistor region. Then, an insulating layer is formed on the entire surface, and as etched back by a reactive ion etching process to form a sidewall spacer. The MOS transistor region and the bipolar transistor region are etched by a wet etching process using the gate electrode and its sidewall spacer as a mask.

    摘要翻译： 在LDD结构的MOS晶体管和双极晶体管的制造方法中，在MOS晶体管区域和双极晶体管区域上形成栅极绝缘层。 然后，在MOS晶体管区域上形成栅电极。 然后，在整个表面上形成绝缘层，并且通过反应离子蚀刻工艺回蚀刻形成侧壁间隔物。 通过使用栅电极及其侧壁间隔物作为掩模的湿式蚀刻工艺来蚀刻MOS晶体管区域和双极晶体管区域。

    Process for forming electrodes for semiconductor devices by focused ion beam technology
    17.
    发明授权
    Process for forming electrodes for semiconductor devices by focused ion beam technology 失效
    通过聚焦离子束技术形成半导体器件电极的工艺

    公开(公告)号：US5043290A

    公开(公告)日：1991-08-27

    申请号：US338274

    申请日：1989-04-14

    申请人： Tadashi Nishioka ,  Yoji Mashiko ,  Hiroaki Morimoto ,  Hiroshi Koyama

    发明人： Tadashi Nishioka ,  Yoji Mashiko ,  Hiroaki Morimoto ,  Hiroshi Koyama

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76877 ,  Y10S148/02 ,  Y10S148/05 ,  Y10S148/131 ,  Y10S148/158

    摘要： A process for forming electrodes for semiconductor devices having a semiconductor substrate and an electrically conductive portion covered and protected by an electrically insulating coating. The process includes the steps of forming an electrically conductive film on the electrically insulating coating, forming an electrode to be connected to an external circuit on the electrically conductive film at a position overlying the electrically conductive portion by exposing portions of the electrically insulating coating and the first electrically conductive film to a converged ion beam, electrically connecting the electrode to the exposed portions of the electrically conductive film, and removing the portions of the electrically conductive film not covered by the electrode. As a result, the likelihood of breakdown of the internal circuit of the semiconductor device connected to the electrically conductive portion while the electrode is being formed is greatly reduced.

    Method for separating monolithically produced laser diodes
    19.
    发明授权
    Method for separating monolithically produced laser diodes 失效
    分离单片产生的激光二极管的方法

    公开(公告)号：US4904617A

    公开(公告)日：1990-02-27

    申请号：US236476

    申请日：1988-08-25

    申请人： Markus Muschke

    发明人： Markus Muschke

    IPC分类号： H01L21/301 ,  H01L21/304 ,  H01L33/00 ,  H01S5/00 ,  H01S5/02 ,  H01S5/026

    CPC分类号： H01L33/005 ,  H01L21/304 ,  H01S5/0201 ,  H01S5/0202 ,  H01S5/0203 ,  Y10S148/051 ,  Y10S148/095 ,  Y10S148/131

    摘要： A method for separating laser diodes. The diodes are monolithically produced from a semiconductor substrate wafer which through an epitaxy process has been provided with a layer sequence suitable for laser operation. First, the semiconductor substrate wafer is covered with a first mask which defines the interspaces between the mirrors of adjacent laser diodes. Then the mirror surfaces are etched out of the semiconductor substrate wafer. Thereafter, the wafer is covered with a second mask for defining separation trench areas between the mirror surfaces of adjacent laser diodes and for protecting the remaining wafer parts. Then, separation are etched into the trench area. Finally, the laser diodes are separated by breaking the wafer along the trenches. In a preferred embodiment, the wafer thickness is at most twice the distance between the mirror surfaces of adjacent laser diodes and the trench depth is at least one fourth of the wafer thickness.

    摘要翻译： 一种分离激光二极管的方法。 二极管由半导体衬底晶片单片制造，其通过外延工艺提供了适合于激光器操作的层序列。 首先，用限定相邻激光二极管的反射镜之间的间隙的第一掩模覆盖半导体衬底晶片。 然后将镜面蚀刻出半导体衬底晶片。 此后，用第二掩模覆盖晶片，用于限定相邻激光二极管的镜面之间的分隔沟槽区域并用于保护剩余的晶片部分。 然后，分离被蚀刻到沟槽区域中。 最后，通过沿着沟槽断开晶片来分离激光二极管。 在优选实施例中，晶片厚度是相邻激光二极管的反射镜表面之间的距离的两倍，并且沟槽深度是晶片厚度的至少四分之一。