公开(公告)号：US09575835B2

公开(公告)日：2017-02-21

申请号：US14692092

申请日：2015-04-21

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Suresh N. Rajan ,  Ian P. Shaeffer ,  Frederick A. Ware ,  Wayne F. Ellis

IPC: G06F11/10 ,  G11C29/44

CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G06F11/108 ,  G11C11/40 ,  G11C29/24 ,  G11C29/42 ,  G11C29/44 ,  G11C29/50016

Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.

Abstract translation: 动态随机存取存储器（DRAM）阵列被配置用于阵列的子集的选择性修复和纠错。 将纠错码（ECC）提供给阵列的选定子集，以保护检测到一个或多个弱存储器单元的行或部分行的存储单元。 通过向存储器阵列的边缘添加感测放大器条纹，阵列的相邻边缘段用于存储与阵列的受保护子集相关联的ECC信息。 位更换也适用于有缺陷的存储单元。 通过有选择地执行ECC而不是整个阵列，在面积和能量消耗方面，以阵列的最低成本保持存储器阵列的完整性。

公开(公告)号：US09570126B2

公开(公告)日：2017-02-14

申请号：US15138424

申请日：2016-04-26

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/00 ,  G11C7/12 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22

CPC classification number: G11C7/1039 ,  G11C5/025 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

Abstract translation: 存储器组件内的行激活操作相对于子行执行，而不是完整的存储行，以减少功耗。 此外，代替激活响应于行命令的子代码，延迟激活操作被延迟，直到接收到指定要执行的列操作的列命令和被激活的子代。

公开(公告)号：US09521338B2

公开(公告)日：2016-12-13

申请号：US14355814

申请日：2012-11-08

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  David Geoffrey Stork ,  Jie Shen ,  Yeuyong Wang ,  Marko Aleksic

IPC: H04N5/353 ,  H04N5/335 ,  H04N5/3745 ,  H04N5/369

CPC classification number: H04N5/353 ,  H04N5/3355 ,  H04N5/3696 ,  H04N5/37455 ,  H04N5/37457

Abstract: In an integrated-circuit image sensor, binary sample values are read out from an array of pixels after successive sampling intervals that collectively span an image exposure interval and include at least two sampling intervals of unequal duration. Each pixel of the array is conditionally reset after each of the successive sampling intervals according to whether the pixel yields a binary sample in a first state or a second state.

Abstract translation: 在集成电路图像传感器中，在连续的采样间隔之后从像素阵列中读出二进制采样值，该采样间隔共同跨越图像曝光间隔并且包括至少两个不等长度的采样间隔。 根据该像素是否产生处于第一状态或第二状态的二进制样本，阵列的每个像素在每个连续采样间隔之后有条件地重置。

公开(公告)号：US20160198108A1

公开(公告)日：2016-07-07

申请号：US14989580

申请日：2016-01-06

Applicant: Rambus Inc.

Inventor： Michael Guidash ,  Jay Endsley ,  John Ladd ,  Thomas Vogelsang ,  Craig M. Smith

IPC: H04N5/374 ,  H04N5/376 ,  H04N5/378 ,  H04N5/365

CPC classification number: H04N5/374 ,  H01L27/14643 ,  H04N5/3577 ,  H04N5/365 ,  H04N5/3765 ,  H04N5/378

Abstract: A pixel within a pixel array of an integrated-circuit image sensor outputs an analog signal representative of accumulated photocharge. First and second analog-to-digital conversions of the analog signal are initiated while the pixel is outputting the analog signal, the first analog-to-digital conversion corresponding to a low-light range of photocharge accumulation within the pixel and the second analog-to-digital conversion corresponding to a brighter-light range of photocharge accumulation within the pixel.

Abstract translation: 集成电路图像传感器的像素阵列内的像素输出表示累积光电荷的模拟信号。 当像素输出模拟信号时，开始模拟信号的第一和第二模拟 - 数字转换，第一模数转换对应于像素内的光电荷累积的低光范围和第二模拟 - 数字转换， 对应于像素内的光电荷累积的较亮光范围的数字转换。

公开(公告)号：US20160118424A1

公开(公告)日：2016-04-28

申请号：US14898054

申请日：2014-06-09

Applicant: Rambus Inc.

Inventor： Michael Guidash ,  Thomas Vogelsang

IPC: H01L27/146

CPC classification number: H01L27/14614 ,  H01L27/14605 ,  H01L27/1461 ,  H01L27/14636 ,  H01L27/14641 ,  H01L27/14643 ,  H04N5/347 ,  H04N5/37457 ,  H04N5/378

Abstract: In a pixel array within an integrated-circuit image sensor, a pixel (870) includes a photodetector (260) and floating diffusion (262) formed within a substrate. First (881) and second (883) gate elements are disposed adjacent one another over a region (885) of the substrate between the photodetector and the floating diffusion and coupled respectively to a row line (TGr) that extends in a row direction within the pixel array and a column line (TGc) that extends in a column direction within the pixel array.

Abstract translation: 在集成电路图像传感器内的像素阵列中，像素（870）包括形成在衬底内的光电检测器（260）和浮动扩散（262）。 第一（881）和第二（883）栅极元件彼此相邻设置在光电检测器和浮动扩散之间的衬底的区域（885）上，并分别耦合到在行方向上延伸的行线（TGr） 像素阵列和在像素阵列内的列方向上延伸的列线（TGc）。

公开(公告)号：US20160028985A1

公开(公告)日：2016-01-28

申请号：US14772311

申请日：2014-03-14

Applicant: RAMBUS INC.

Inventor： Thomas Vogelsang ,  Michael Guidash ,  Song Xue ,  Maxim Smirnov ,  Craig M. Smith ,  Jay Endsley ,  James E. Harris

IPC: H04N5/3745 ,  H04N5/376

CPC classification number: H04N5/3745 ,  H01L27/14634 ,  H01L27/14641 ,  H04N5/347 ,  H04N5/376

Abstract: An image sensor architecture with multi-bit sampling is implemented within an image sensor system. A pixel signal produced in response to light incident upon a photosensitive element is converted to a multiple-bit digital value representative of the pixel signal. If the pixel signal exceeds a sampling threshold, the photosensitive element is reset. During an image capture period, digital values associated with pixel signals that exceed a sampling threshold are accumulated into image data.

Abstract translation: 在图像传感器系统中实现具有多位采样的图像传感器架构。 响应于入射到感光元件上的光而产生的像素信号被转换成表示像素信号的多位数字值。 如果像素信号超过采样阈值，则光敏元件被复位。 在图像捕获期间，与超过采样阈值的像素信号相关联的数字值被累积到图像数据中。

公开(公告)号：US09116781B2

公开(公告)日：2015-08-25

申请号：US13653033

申请日：2012-10-16

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Brent Haukness ,  Stephen Charles Bowyer

IPC: G06F12/00 ,  G06F13/16

CPC classification number: G11C11/4096 ,  G06F12/00 ,  G06F13/1694 ,  G11C11/4087 ,  G11C11/4091

Abstract: Embodiments generally relate to a command protocol and/or related circuits and apparatus for communication between a memory device and a memory controller. In one embodiment, the memory controller includes an interface for transmitting commands to the memory device, wherein the memory device includes bitline multiplexers, and accessing of memory cells within the memory device is carried out by a command protocol sequence that includes a wordline selection, followed by bitline selections by the bitline multiplexers. In another embodiment, a memory device includes bitline multiplexers and further includes an interface for receiving a command protocol sequence that specifies a wordline selection followed by bitline selections by the bitline multiplexers.

Abstract translation: 实施例通常涉及用于存储器设备和存储器控制器之间的通信的命令协议和/或相关电路和装置。 在一个实施例中，存储器控制器包括用于向存储器件发送命令的接口，其中存储器件包括位线复用器，并且通过包括字线选择的命令协议序列执行存储器设备内的存储器单元的访问， 通过位线多路复用器的位线选择。 在另一个实施例中，存储器件包括位线多路复用器，并且还包括接口，用于接收指定字线选择的命令协议序列，随后由位线复用器进行位线选择。

公开(公告)号：US20150033044A1

公开(公告)日：2015-01-29

申请号：US14452373

申请日：2014-08-05

Applicant: Rambus Inc.

Inventor： Ely Tsern ,  Thomas Vogelsang ,  Craig Hampel ,  Scott C. Best

IPC: G06F3/06 ,  G06F1/26 ,  G11C5/14

CPC classification number: G06F3/0625 ,  G06F1/266 ,  G06F3/0634 ,  G06F3/0673 ,  G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

Abstract: A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.

Abstract translation: 内存系统支持高性能和低功耗模式。 存储器系统包括存储器核和核心接口。 存储器内核采用在两种模式下保持相同的核心电源电压。 核心接口的电源电压和信号速率可以缩小以节省功耗。 存储器核心和核心接口电平之间的电平移位器根据需要移位信号以适应不同模式下核心接口所使用的信令电压。

公开(公告)号：US20140376324A1

公开(公告)日：2014-12-25

申请号：US14241407

申请日：2012-08-31

Applicant: RAMBUS INC.

Inventor： Thomas Vogelsang ,  William N. Ng ,  Frederick A. Ware

IPC: G11C29/04 ,  G11C8/10 ,  G01R31/28

CPC classification number: G11C29/04 ,  G01R31/2851 ,  G11C8/10 ,  G11C29/025 ,  H01L22/34 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/1434 ,  H01L2924/00

Abstract: Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TS V to at least one of a test input and a test evaluation circuit.

Abstract translation: 实施例通常涉及具有硅通孔（TSV）的集成电路器件。 在一个实施例中，集成电路（IC）装置包括TSV的场和地址解码器，其将至少一个TSV可选地耦合到测试输入和测试评估电路中的至少一个。 在另一实施例中，一种方法包括从至少一个IC器件中的TSV领域中选择一个或多个TSV，以及将每个选择的TS V耦合到测试输入和测试评估电路中的至少一个。

公开(公告)号：US20140219008A1

公开(公告)日：2014-08-07

申请号：US14245905

申请日：2014-04-04

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C11/401

CPC classification number: G11C11/401 ,  H01L27/10885 ,  H01L27/10888

Abstract: A dynamic random access memory (DRAM) device has a hierarchical bitline structure with local bitlines and global bitlines formed on different metal layers. The local bitlines are separated into a plurality of local bitline sections, and bitline isolation switches are configured to connect or disconnect the local bitline sections to or from the global bitlines. As a result, the local bitlines with higher per-length capacitance can be made shorter, since the global bitline with lower per-length capacitance is used to route the signal from the cell capacitances of the memory cells to the remote sense amplifiers.

Abstract translation: 动态随机存取存储器（DRAM）器件具有分层位线结构，其中局部位线和在不同金属层上形成的全局位线。 局部位线被分成多个本地位线部分，并且位线隔离开关被配置为将本地位线部分连接到全局位线或从全局位线断开连接。 结果，由于具有较低的每长度电容的全局位线用于将来自存储器单元的单元电容的信号路由到远程读出放大器，所以可以使具有较高每个长度电容的局部位线更短。