公开(公告)号：US20130334675A1

公开(公告)日：2013-12-19

申请号：US13919536

申请日：2013-06-17

Applicant: STMicroelectronics S.r.I.

Inventor： Federico Giovanni ZIGLIOLI ,  Alberto PAGANI

IPC: H01L23/495 ,  H01L21/50

CPC classification number: H01L23/642 ,  H01L21/441 ,  H01L21/50 ,  H01L21/561 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49537 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/5385 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/105 ,  H01L28/40 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/07802 ,  H01L2924/00

Abstract: An embodiment of a packaged semiconductor device includes a communication pad formed in a side surface, which is operatively coupled to a communication circuit so as to enable the establishing of a wireless communication channel to an adjacently positioned packaged semiconductor device. The communication pad may be formed upon cutting a block including the packaged semiconductor device and an appropriately positioned and dimensioned conductor. Thus, well-established techniques for incorporating a lead frame or any other conductive system in a package may be applied in order to impart wireless lateral connectivity to packaged semiconductor devices in an electronic system.

Abstract translation: 封装半导体器件的实施例包括形成在侧表面中的通信焊盘，其可操作地耦合到通信电路，以便能够建立到相邻定位的封装半导体器件的无线通信信道。 可以在切割包括封装的半导体器件的块和适当定位和尺寸的导体时形成通信焊盘。 因此，可以应用用于将引线框架或任何其它导电系统并入封装中的完善的技术，以便赋予电子系统中的封装半导体器件无线横向连接性。

公开(公告)号：US20130330836A1

公开(公告)日：2013-12-12

申请号：US13902468

申请日：2013-05-24

Applicant: STMicroelectronics S.r.I.

Inventor： Lucio Renna ,  Clelia Carmen Galati ,  Natalia Maria Rita Spinella ,  Piero Giorgio Fallica

IPC: G01N21/64

CPC classification number: G01N21/6428 ,  G01N21/6454 ,  G01N33/551

Abstract: A diagnostic device includes a photodiode (2) formed by a body (10) of semiconductor material having a first surface (6a), an integrated optical structure (30) on the first surface and having a second surface (34a), and at least one detection region (50) on the second surface. The at least one detection region includes at least one receptor (52) that binds to a corresponding target molecule (MB) that can be mated with a corresponding marker (54), which, when excited by radiation having a first wavelength (λe), emits radiation having a second wavelength (λf) that can be detected by the photodiode. The integrated optical structure includes at least a first layer (34, 62) of a first material having a first refractive index (n1). The first layer has a thickness substantially equal to an integer and odd multiple of one fourth of the first wavelength (λe) divided by the first refractive index.

Abstract translation: 诊断装置包括由半导体材料的本体（10）形成的光电二极管，所述半导体材料具有第一表面（6a），在第一表面上具有集成光学结构（30），并具有第二表面（34a），并且至少 在第二表面上的一个检测区域（50）。 所述至少一个检测区域包括至少一个与相应的靶分子（MB）结合的受体（52），所述靶分子（MB）可以与相应的标记物（54）相配合，所述对应标记物当被具有第一波长的辐射激发时， 发射具有可由光电二极管检测的第二波长（羔羊）的辐射。 集成光学结构至少包括具有第一折射率（n1）的第一材料的第一层（34,62）。 第一层具有基本上等于第一波长（lambdae）四分之一的整数和奇数倍除以第一折射率的厚度。

公开(公告)号：US20130279813A1

公开(公告)日：2013-10-24

申请号：US13869652

申请日：2013-04-24

Applicant: STMICROELECTRONICS S.R.I.

Inventor： Danilo Pietro Pau ,  Mirko Falchetto

IPC: G06K9/46

CPC classification number: G06K9/6228 ,  G06K9/32 ,  G06K9/46 ,  G06K2009/363 ,  G06T7/33 ,  G06T7/337 ,  H04N19/57

Abstract: Image-processing apparatus and methods to adaptively vary an interest point threshold value and control a number of interest points identified in an image frame are described. Sub-regions of an image frame may be processed in a sequence, and an interest point threshold value calculated for each sub-region. The calculated value of the interest point threshold may depend upon pre-selected values and values determined from the processing of one or more prior sub-regions. By using adaptive thresholding, a number of interest points detected for each frame in a sequence of image frames may remain substantially constant, even though objects within the frames may vary appreciably.

Abstract translation: 描述用于自适应地改变兴趣点阈值并控制在图像帧中识别的兴趣点数量的图像处理装置和方法。 图像帧的子区域可以按顺序处理，并且为每个子区域计算出的兴趣点阈值。 所计算的兴趣点阈值可以取决于从一个或多个先前子区域的处理确定的预先选择的值和值。 通过使用自适应阈值处理，对于图像帧序列中的每个帧检测的多个感兴趣点可以保持基本上恒定，即使帧内的对象可能明显变化。

公开(公告)号：US20130241025A1

公开(公告)日：2013-09-19

申请号：US13801354

申请日：2013-03-13

Applicant: STMICROELECTRONICS S.R.I.

Inventor： Alberto PAGANI

IPC: H01L27/02 ,  H01L21/768

CPC classification number: H01L27/0203 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L22/22 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49833 ,  H01L23/66 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/6677 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/02321 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/06187 ,  H01L2224/08137 ,  H01L2224/08146 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/14183 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/28105 ,  H01L2224/29024 ,  H01L2224/30183 ,  H01L2224/32145 ,  H01L2224/32227 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/48175 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73251 ,  H01L2224/82106 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06531 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15159 ,  H01L2924/207 ,  H05K1/181 ,  H05K1/189 ,  H05K2201/10515 ,  Y02P70/611 ,  H01L2224/02 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2224/32 ,  H01L2224/19 ,  H01L2924/00

Abstract: An embodiment of an electronic system may be provided so as to have superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in PCBs coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced.

Abstract translation: 可以提供电子系统的实施例，以便通过实现例如在系统中的有线和/或无线通信信道的基础上提供至少提供水平通信的通信机制来具有优异的耦合。 因此，通过增强电子系统中的垂直和水平通信能力，可以实现减小的总体尺寸，同时降低耦合到电子系统的PCB的复杂性。 以这种方式，可以提高复杂电子系统的总体制造成本和可靠性。

公开(公告)号：US20130227158A1

公开(公告)日：2013-08-29

申请号：US13775885

申请日：2013-02-25

Applicant: STMicroelectronics S.r.I.

Inventor： Konstantin MILLER ,  Emanuele QUACCHIO

IPC: H04L29/06

CPC classification number: H04L65/60 ,  H04L65/4084 ,  H04L65/4092 ,  H04L65/602 ,  H04L65/80

Abstract: In an embodiment, a control unit includes a determiner and a requestor. The determiner is configured to determine media-data rate in response to the network throughput and one of multiple fill ranges to which a level of a buffer corresponds, and the requestor is configured to request a media-file segment having the determined media-data rate. For example, such a control unit may be able to control the streaming of a video file in a way that reduces or prevents buffer underflows (i.e., video “freezes”), reduces the start-up delay, and that reduces the frequency of changes from one quality level (e.g., resolution) to another quality level, while streaming the highest-quality version of the video file that the data throughput allows. That is, the control unit seeks to maximize the streamed video quality while minimizing the number of buffer underflows, the number of changes in the streamed resolution caused by changes in the throughput, and the start-up delay.

Abstract translation: 在一个实施例中，控制单元包括确定器和请求者。 确定器被配置为响应于网络吞吐量和缓冲器级别对应的多个填充范围中的一个来确定媒体数据速率，并且请求者被配置为请求具有确定的媒体数据速率的媒体文件段 。 例如，这样的控制单元可以能够以减少或防止缓冲器下溢（即，视频“冻结”）的方式来控制视频文件的流式传输，减少启动延迟，并且减少变化的频率 从一个质量水平（例如，分辨率）到另一个质量水平，同时流式传输数据吞吐量允许的最高质量的视频文件。 也就是说，控制单元寻求使传输的视频质量最大化，同时最小化缓冲器下溢的数量，由吞吐量的变化引起的流分辨率的改变的数量以及启动延迟。

公开(公告)号：US20130159713A1

公开(公告)日：2013-06-20

申请号：US13735876

申请日：2013-01-07

Applicant: STMicroelectronics S.r.I. ,  Hewlett-Packard Development Company

Inventor： Liqun CHEN ,  Keith HARRISON ,  Guido Marco BERTONI ,  Pasqualina FRAGNETO ,  Gerardo PELOSI

IPC: H04L9/08

CPC classification number: H04L9/08 ,  H04L9/3073 ,  H04L9/321 ,  H04L2209/80 ,  H04W12/06

Abstract: An authentication method of a first module by a second module includes the steps of generating a first random datum by the second module to be sent to the first module, generating a first number by the first module starting from the first datum and by way of a private key, and generating a second number by the second module to be compared with the first number, so as to authenticate the first module. The step of generating the second number is performed starting from public parameters and is independent of the step of generating the first number.

Abstract translation: 通过第二模块的第一模块的认证方法包括以下步骤：由第二模块生成要发送到第一模块的第一随机数据，由第一模块从第一数据开始生成第一数字，并通过 私钥，并且由第二模块生成与第一号码进行比较的第二号码，以便认证第一模块。 从公共参数开始执行产生第二数量的步骤，并且独立于生成第一个数字的步骤。

公开(公告)号：US20040268275A1

公开(公告)日：2004-12-30

申请号：US10850834

申请日：2004-05-21

Applicant: STMicroelectronics S.r.I.

Inventor： Paolo Cappelletti ,  Alfonso Maurelli

IPC: H01L021/44 ,  G06F017/50

CPC classification number: H01L22/34 ,  G01R31/2853 ,  G01R31/2884 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A test chip performs measurements to evaluate the performances of interconnects. In particular, the statistical failure distribution, the electromigration and the leakage current are measured. An algorithm detects a via failure at any of the available n metal layers. The test chip includes a ROM memory array. The vias to be measured are formed in the columns of the array. Via or contact failures are detected by forcing a predetermined current through both an array column and a reference column. The failure analysis is obtained by comparing the resulting voltage drops.

Abstract translation: 测试芯片执行测量以评估互连的性能。 特别地，测量统计失效分布，电迁移和漏电流。 算法检测任何可用的n个金属层的通孔故障。 测试芯片包括ROM存储器阵列。 要测量的通孔在阵列的列中形成。 通过强制通过阵列列和参考列的预定电流来检测通过或接触故障。 通过比较所得的电压降来获得故障分析。

公开(公告)号：US20040225869A1

公开(公告)日：2004-11-11

申请号：US10776024

申请日：2004-02-10

Applicant: STMicroelectronics S.r.I.

Inventor： Andrea Pagni ,  Fabrizio Lucini ,  Danilo Pietro Pau ,  Antonio Maria Borneo ,  Vittorio Zaccaria

IPC: G06F009/44

CPC classification number: G06F9/30174 ,  G06F9/30098 ,  G06F9/30189 ,  G06F9/3879

Abstract: A procedure for translating ARM instructions of a first set into instructions of a second set for execution on an LX processor comprising a core provides a first set of registers corresponding to the ARM instructions and a second set of registers corresponding to the instructions that can be executed on the LX processor. Each register of the first set is mapped in a corresponding register of the second set designed to emulate the behavior of the first register, obtaining a unique independent translation of the first set into the second set. The translation is performed by a translation device external to the LX core without altering the core, and the translation operating without accessing resources of the core, by the translating device intercepting accesses of the core to the storage area reserved to the ARM instructions.

Abstract translation: 用于将第一集合的ARM指令转换为用于在包括核的LX处理器上执行的第二集合的指令的过程提供对应于ARM指令的第一组寄存器和对应于可执行的指令的第二组寄存器 在LX处理器上。 将第一组的每个寄存器映射到第二组的对应寄存器中，该寄存器被设计为模拟第一寄存器的行为，从而获得第一集合到第二集合中的唯一的独立转换。 翻译由LX核心外部的翻译设备执行，而不改变核心，并且通过翻译设备将核心的访问拦截到保留给ARM指令的存储区域，而不会访问核心的资源。

公开(公告)号：US20040213471A1

公开(公告)日：2004-10-28

申请号：US10424141

申请日：2003-04-25

Applicant: STMicroelectronics S.r.I.

Inventor： Mauro De Ponti ,  Marco Ferretti ,  Matteo Boffadossi

IPC: G06K009/36 ,  G06K009/46

CPC classification number: H04N19/93 ,  H04N19/13 ,  H04N19/14 ,  H04N19/42 ,  H04N19/90 ,  H04N19/91

Abstract: A method of compressing a stream of pixel data relative a two-dimensional object, pixels of which are scanned by rows from a source device to a receiver device, includes defining an extended context window to include a pair of pixels following a last encoded pixel on the row being scanned and the respective triplets of neighboring pixels belonging to the preceding row. The method includes defining a first distinct context array of pixels of the extended context window for the pixel of the pair immediately following the last encoded pixel, and a second context array of pixels of the extended context window for the other pixel of the pair. An extended context value relative to each pixel of the pair is calculated, and the extended context value relative to a first pixel immediately following the last encoded pixel is compared with an extended threshold. If the extended context value is less than the extended threshold, then encoding the first and second pixels of the pair, and if the extended context value relative to the first pixel of the pair exceeds the extended threshold, then carrying out simultaneously a parallel processing and encoding of both pixels according to an encoding routine.

Abstract translation: 压缩像素数据相对于二维对象（其像素从源设备被扫描的行）到接收器设备的方法，包括定义扩展上下文窗口以包括在最后编码像素之后的一对像素 正在被扫描的行以及属于前一行的相邻像素的相应三元组。 该方法包括为紧邻在最后编码像素之后的对的像素定义扩展上下文窗口的第一个不同上下文阵列的像素，以及该对的另一个像素的扩展上下文窗口的第二上下文阵列的扩展上下文窗口。 计算相对于该对中的每个像素的扩展上下文值，并将相对于紧接在最后编码像素之后的第一像素的扩展上下文值与扩展阈值进行比较。 如果扩展上下文值小于扩展阈值，则对该对的第一和第二像素进行编码，并且如果相对于该对的第一像素的扩展上下文值超过扩展阈值，则同时执行并行处理和 根据编码程序编码两个像素。

公开(公告)号：US20040208063A1

公开(公告)日：2004-10-21

申请号：US10675221

申请日：2003-09-30

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Giovanni Campardo

IPC: G11C011/34 ,  G11C016/04

CPC classification number: G11C29/82 ,  G11C16/04 ,  G11C16/16 ,  G11C29/44 ,  G11C2029/1208

Abstract: The invention relates to a method for erasing non-volatile memory cells, and to a corresponding non-volatile memory device of the programmable and electrically erasable type implementing the method, and comprising a memory cell array organized in a row-and-column layout, and divided in array sectors, including at least one row decode circuit portion being supplied positive and negative voltages. The method is applied whenever the issue of the erase algorithm is negative, and comprises the following steps: forcing an incompletely erased sector into a read condition; scanning the rows of said sector to check for the possible presence of a spurious current indicating a fail state; identifying and electrically isolating the failed row; re-addressing from said failed row to a redundant row provided in the same sector; re-starting the erase algorithm.

Abstract translation: 本发明涉及一种用于擦除非易失性存储单元的方法，以及实现该方法的可编程和电可擦除类型的相应非易失性存储器件，并且包括以行和列布局组织的存储单元阵列， 并且被划分成阵列扇区，包括至少一个行解码电路部分被提供正和负电压。 每当擦除算法的问题为负时，该方法被应用，并且包括以下步骤：强制将未完全擦除的扇区进入读取状态; 扫描所述扇区的行以检查指示故障状态的寄生电流的可能存在; 识别和电隔离失败的行; 从所述故障行重新寻址到在同一扇区中提供的冗余行; 重新启动擦除算法。