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    Process for PECVD of silicon oxide using TEOS decomposition
    231.
    再颁专利
    Process for PECVD of silicon oxide using TEOS decomposition 失效

    公开(公告)号：USRE36623E

    公开(公告)日：2000-03-21

    申请号：US752972

    申请日：1996-12-02

    Applicant: David Nin-Kou Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    Inventor： David Nin-Kou Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    IPC: C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  C23C16/509 ,  C23C16/54 ,  H01L21/314 ,  H01L21/316 ,  H05H1/24

    CPC classification number: C23C16/45565 ,  C23C16/402 ,  C23C16/455 ,  C23C16/45521 ,  C23C16/5096 ,  C23C16/54 ,  H01J37/32082 ,  H01J37/3244 ,  H01L21/31604

    Abstract: A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surface. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the sane reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

    Plasma-enhanced CVD process using TEOS for depositing silicon oxide
    235.
    发明授权
    Plasma-enhanced CVD process using TEOS for depositing silicon oxide 失效

    公开(公告)号：US5362526A

    公开(公告)日：1994-11-08

    申请号：US645999

    申请日：1991-01-23

    Applicant: David N. Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    Inventor： David N. Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    IPC: C23C16/48 ,  C23C16/04 ,  C23C16/40 ,  C23C16/42 ,  C23C16/44 ,  C23C16/455 ,  C23C16/46 ,  C23C16/50 ,  C23C16/509 ,  C23C16/54 ,  C23F4/00 ,  C30B25/14 ,  H01L21/205 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/314 ,  H01L21/316 ,  H01L21/683 ,  B05D3/06

    CPC classification number: C23C16/45565 ,  C23C16/402 ,  C23C16/455 ,  C23C16/45521 ,  C23C16/5096 ,  C23C16/54 ,  H01J37/32082 ,  H01J37/3244 ,  H01L21/31604

    Abstract: A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

    Variable RF power splitter
    236.
    发明授权
    Variable RF power splitter 失效
    可变RF功率分配器

    公开(公告)号：US5349313A

    公开(公告)日：1994-09-20

    申请号：US140338

    申请日：1993-10-22

    Applicant: Kenneth S. Collins ,  John R. Trow ,  Craig A. Roderick

    Inventor： Kenneth S. Collins ,  John R. Trow ,  Craig A. Roderick

    IPC: H03H7/48 ,  H03H11/30 ,  H03H7/38

    CPC classification number: H03H7/48 ,  H01F2029/143

    Abstract: A variable RF power splitter including three serially connected inductors (14, 15, 16) powered by an RF power source (11, 12). Two loads (17, 18), between which the RF power is to be split, are connected to ground from two different points in the inductance string. A variable reactance (19) connected to ground from another point in the inductance string controls the RF power splitting.

    Abstract translation: 一种可变RF功率分配器，包括由RF电源（11,12）供电的三个串联的电感器（14,15,16）。 RF功率要分开的两个负载（17,18）从电感串中的两个不同点连接到地。 从电感串中的另一点连接到地的可变电抗（19）控制RF功率分配。

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