公开(公告)号：US20170140994A1

公开(公告)日：2017-05-18

申请号：US15419346

申请日：2017-01-30

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Ali Khakifirooz ,  Theodorus E. Standaert ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L21/84 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/311 ,  H01L27/088

CPC classification number: H01L21/823437 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785

Abstract: A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

公开(公告)号：US20170092645A1

公开(公告)日：2017-03-30

申请号：US15170134

申请日：2016-06-01

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Xiuyu Cai ,  Sanjay C. Mehta ,  Tenko Yamashita

IPC: H01L27/092 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/306 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method for fabricating a field effect transistor device comprises forming a fin on a substrate, forming a first dummy gate stack and a second dummy gate stack over the fin, forming spacers adjacent to the fin, the first dummy gate stack, and the second dummy gate stack, etching to remove portions of the fin and form a first cavity partially defined by the spacers, depositing an insulator material in the first cavity, patterning a mask over the first dummy gate stack and portions of the fin, etching to remove exposed portions of the insulator material, and epitaxially growing a first semiconductor material on exposed portions of the fin.

公开(公告)号：US20170012042A1

公开(公告)日：2017-01-12

申请号：US15157861

申请日：2016-05-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of forming a semiconductor device that includes forming a plurality of semiconductor pillars. A dielectric spacer is formed between at least one set of adjacent semiconductor pillars. Semiconductor material is epitaxially formed on sidewalls of the adjacent semiconductor pillars, wherein the dielectric spacer obstructs a first portion of epitaxial semiconductor material formed on a first semiconductor pillar from merging with a second portion of epitaxial semiconductor material formed on a second semiconductor pillar.

Abstract translation: 一种形成包括形成多个半导体柱的半导体器件的方法。 在至少一组相邻的半导体柱之间形成介电间隔物。 半导体材料外延地形成在相邻半导体柱的侧壁上，其中电介质间隔物阻挡形成在第一半导体柱上的外延半导体材料的第一部分与形成在第二半导体柱上的第二部分外延半导体材料合并。

公开(公告)号：US09536836B2

公开(公告)日：2017-01-03

申请号：US15167306

申请日：2016-05-27

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/336 ,  H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/285 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/53266 ,  H01L29/6659 ,  H01L29/66643 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An MIS contact structure comprises a layer of semiconductor material, a layer of insulating material having a contact opening formed therein, a layer of contact insulating material having substantially vertically oriented portions and a substantially horizontally oriented portion, the vertically oriented portions of the layer of contact insulating material contacting a portion, but not all, of the sidewalls of the contact opening and the horizontally oriented portion of the layer of contact insulating material contacting the semiconductor layer. A conductive material is positioned on the layer of contact insulating material within the contact opening, the conductive material layer having vertically oriented portions and a horizontally oriented portion and a conductive contact positioned in the contact opening that contacts the uppermost surfaces of the conductive material layer and the layer of contact insulating material.

Abstract translation: MIS接触结构包括半导体材料层，具有形成在其中的接触开口的绝缘材料层，具有基本上垂直取向的部分和基本上水平取向的部分的接触绝缘材料层，接触层的垂直取向部分 绝缘材料接触接触开口的侧壁的部分而不是全部接触半导体层的接触绝缘材料层的水平取向部分。 导电材料位于接触开口内的接触绝缘材料层上，导电材料层具有垂直取向的部分和水平取向的部分，以及定位在接触开口中的导电触点，其接触导电材料层的最上表面， 接触层绝缘材料。

公开(公告)号：US20160372576A1

公开(公告)日：2016-12-22

申请号：US15255628

申请日：2016-09-02

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/0337 ,  H01L21/283 ,  H01L21/3083 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

Abstract: Embodiments of the present invention may include methods of incorporating an embedded etch barrier layer into the replacement metal gate layer of field effect transistors (FETs) having replacement metal gates, as well as the structure formed thereby. The embedded etch stop layer may be composed of embedded dopant atoms and may be formed using ion implantation. The embedded etch stop layer may make the removal of replacement metal gate layers easier and more controllable, providing horizontal surfaces and determined depths to serve as the base for gate cap formation. The gate cap may insulate the gate from adjacent self-aligned electrical contacts.

Abstract translation: 本发明的实施例可以包括将嵌入的蚀刻阻挡层结合到具有替换金属栅极的场效应晶体管（FET）的替换金属栅极层以及由此形成的结构的方法。 嵌入的蚀刻停止层可以由嵌入的掺杂剂原子组成，并且可以使用离子注入形成。 嵌入的蚀刻停止层可以使得替换金属栅极层的移除更容易和更可控，从而提供水平表面和确定的深度以用作栅极盖形成的基底。 栅极帽可以将栅极与相邻的自对准电触头绝缘。

公开(公告)号：US09478634B2

公开(公告)日：2016-10-25

申请号：US14535852

申请日：2014-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/32 ,  H01L21/02

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/31111 ,  H01L21/32 ,  H01L21/32055 ,  H01L21/32133 ,  H01L21/32139 ,  H01L29/66553

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin having an upper surface and a plurality of side surfaces, forming a sacrificial gate structure comprised of a low-density oxide material having a density of less than 1.8 g/cm3 on and in contact with the upper surface and the side surfaces of the fin and a sacrificial gate material positioned on and in contact with the upper surface of the low-density oxide material, and forming a sidewall spacer adjacent the sacrificial gate structure. The method further includes removing the sacrificial gate material so as to thereby expose the low-density oxide material, so as to define a replacement gate cavity, and forming a replacement gate structure in the replacement gate cavity.

Abstract translation: 本文公开的一种说明性方法包括形成具有上表面和多个侧表面的翅片，形成牺牲栅极结构，所述牺牲栅极结构由密度小于1.8g / cm 3的低密度氧化物材料和 与翅片的上表面和侧表面接触，并且牺牲栅材料定位在低密度氧化物材料的上表面上并与低密度氧化物材料的上表面接触，并且形成邻近牺牲栅极结构的侧壁间隔物。 该方法还包括去除牺牲栅极材料，从而暴露低密度氧化物材料，以便限定替换栅极腔，并在替换栅极腔中形成替代栅极结构。

公开(公告)号：US09455330B2

公开(公告)日：2016-09-27

申请号：US14550019

申请日：2014-11-21

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie

IPC: H01L21/44 ,  H01L29/66 ,  H01L21/283 ,  H01L21/308 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/0337 ,  H01L21/283 ,  H01L21/3083 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

Abstract: Embodiments of the present invention may include methods of incorporating an embedded etch barrier layer into the replacement metal gate layer of field effect transistors (FETs) having replacement metal gates, as well as the structure formed thereby. The embedded etch stop layer may be composed of embedded dopant atoms and may be formed using ion implantation. The embedded etch stop layer may make the removal of replacement metal gate layers easier and more controllable, providing horizontal surfaces and determined depths to serve as the base for gate cap formation. The gate cap may insulate the gate from adjacent self-aligned electrical contacts.

Abstract translation: 本发明的实施例可以包括将嵌入的蚀刻阻挡层结合到具有替换金属栅极的场效应晶体管（FET）的替换金属栅极层以及由此形成的结构的方法。 嵌入的蚀刻停止层可以由嵌入的掺杂剂原子组成，并且可以使用离子注入形成。 嵌入的蚀刻停止层可以使得替换金属栅极层的移除更容易和更可控，从而提供水平表面和确定的深度以用作栅极盖形成的基底。 栅极帽可以将栅极与相邻的自对准电触头绝缘。

公开(公告)号：US09431539B2

公开(公告)日：2016-08-30

申请号：US14511715

申请日：2014-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Catherine B. Labelle ,  Xiuyu Cai

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/78 ,  H01L27/12 ,  H01L29/10 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/7849 ,  B82Y10/00 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76283 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66818 ,  H01L29/775

Abstract: A dual-strained Si and SiGe FinFET device with dielectric isolation and a dual-strained nanowire device and methods of forming them are provided. Embodiments include a SiGe SRB formed on a silicon substrate, the SRB having a first region and a second region; a first and a second dielectric isolation layer formed on the first region and on the second region of the SiGe SRB, respectively; a tensile strained Si fin formed on the first dielectric isolation layer; a compressive strained SiGe fin formed on the second dielectric isolation layer; first source/drain regions formed at opposite sides of the tensile strained Si fin; second source/drain regions formed at opposite sides of the compressive strained SiGe fin; a first RMG formed between the first source/drain regions; and a second RMG formed between the second source/drain regions.

Abstract translation: 提供具有绝缘隔离的双应变Si和SiGe FinFET器件和双应变纳米线器件及其形成方法。 实施例包括形成在硅衬底上的SiGe SRB，SRB具有第一区域和第二区域; 分别形成在SiGe SRB的第一区域和第二区域上的第一和第二介电隔离层; 形成在第一介电隔离层上的拉伸应变Si翅片; 形成在所述第二介电隔离层上的压缩应变SiGe鳍; 形成在拉伸应变Si翅片的相对侧的第一源极/漏极区域; 形成在压缩应变SiGe翅片的相对侧的第二源极/漏极区域; 形成在第一源/漏区之间的第一RMG; 以及形成在第二源/漏区之间的第二RMG。

公开(公告)号：US09419137B1

公开(公告)日：2016-08-16

申请号：US14641809

申请日：2015-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Abner Bello ,  Xiuyu Cai ,  Hugh Porter ,  Daniel Pham

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/324 ,  H01L21/3105 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/7847 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924

Abstract: A method of straining fins of a FinFET device by using a stress memorization film and the resulting device are provided. Embodiments include providing a plurality of bulk Si fins, the plurality of bulk Si fins having a recessed oxide layer therebetween; forming a stress memorization layer over the plurality of bulk Si fins and the recessed oxide layer; annealing the stress memorization layer, the plurality of bulk Si fins, and the recessed oxide layer; and removing the stress memorization layer.

Abstract translation: 提供了通过使用应力记忆膜来制造FinFET器件的鳍片的方法以及所得到的器件。 实施例包括提供多个体积Si散热片，所述多个本体Si散热片在其间具有凹陷的氧化物层; 在所述多个体积Si散热片和所述凹陷氧化物层上形成应力记忆层; 退火应力记忆层，多个体积Si散热片和凹陷氧化物层; 并去除应力记忆层。

公开(公告)号：US20160149015A1

公开(公告)日：2016-05-26

申请号：US14550019

申请日：2014-11-21

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/283 ,  H01L21/308

CPC classification number: H01L29/66545 ,  H01L21/0337 ,  H01L21/283 ,  H01L21/3083 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

Abstract: Embodiments of the present invention may include methods of incorporating an embedded etch barrier layer into the replacement metal gate layer of field effect transistors (FETs) having replacement metal gates, as well as the structure formed thereby. The embedded etch stop layer may be composed of embedded dopant atoms and may be formed using ion implantation. The embedded etch stop layer may make the removal of replacement metal gate layers easier and more controllable, providing horizontal surfaces and determined depths to serve as the base for gate cap formation. The gate cap may insulate the gate from adjacent self-aligned electrical contacts.