公开(公告)号：US09455689B2

公开(公告)日：2016-09-27

申请号：US14547684

申请日：2014-11-19

Applicant: STMICROELECTRONICS SA ,  UNIVERSITY OF TWENTE

Inventor： Andreia Cathelin ,  Bram Nauta

IPC: H01L21/8238 ,  H01L29/66 ,  H03K3/012 ,  H01L21/84 ,  H01L29/786 ,  H01L27/12

CPC classification number: H03K3/012 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603 ,  H01L29/78648

Abstract: A Silicon On Insulator current source array includes input control for receiving a control voltage, a first reference input for receiving a first reference voltage, and a second reference input for receiving a second reference voltage. A chain of several Silicon On Insulator MOS transistors, of the same type, have control electrodes all connected to the input control, first conduction electrodes are all connected to the first reference input, and second conduction electrodes are respectively connected to the second reference input through several load circuits respectively configured to be traversed by several currents when the several transistors are ON upon application of the control voltage on the input control. An input bias is coupled to a semiconductor well located below an insulating buried layer located below the chain of transistors for receiving a biasing voltage difference.

Abstract translation: 硅绝缘体电流源阵列包括用于接收控制电压的输入控制，用于接收第一参考电压的第一参考输入和用于接收第二参考电压的第二参考输入。 具有相同类型的多个绝缘体硅MOS晶体管的链条具有全部连接到输入控制的控制电极，第一导电电极全部连接到第一参考输入，第二导电电极分别连接到第二参考输入 当在输入控制上施加控制电压时，当几个晶体管导通时，多个负载电路分别被配置为被几个电流穿过。 输入偏置耦合到位于晶体管链下方的绝缘掩埋层下方的半导体阱，用于接收偏置电压差。

公开(公告)号：US09423580B2

公开(公告)日：2016-08-23

申请号：US14637559

申请日：2015-03-04

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Robert Manouvrier ,  Estelle Batail

IPC: G02F1/01 ,  G02F1/035 ,  G02F1/295 ,  G02B6/12 ,  G02B6/10 ,  G02B6/42 ,  G02B6/13 ,  H01L21/768 ,  H01L49/02 ,  G02F1/025 ,  H01L27/02

CPC classification number: G02B6/4275 ,  G02B6/13 ,  G02F1/025 ,  G02F2202/22 ,  H01L21/768 ,  H01L27/0248 ,  H01L28/40

Abstract: An ESD protection device for an electro-optical device may include an optical waveguide segment being in semiconductor material and including a central zone of a first conductivity type, and first and second wings of a second conductivity type different from the first conductivity type and being integral with the central zone. The ESD protection device may include a first conduction terminal on the first wing for defining a first protection terminal, a second conduction terminal on the second wing for defining a second protection terminal, and a resistive contact structure of the first conductivity type having a transverse arm integral with the central zone, and an end in ohmic contact with the first conduction terminal, the resistive contact structure being electrically insulated from the first wing.

Abstract translation: 用于电光装置的ESD保护装置可以包括半导体材料中的光波导段，并且包括第一导电类型的中心区，以及不同于第一导电类型的第二导电类型的第一和第二翼， 与中央区。 ESD保护装置可以包括在第一翼上的用于限定第一保护端子的第一导电端子，用于限定第二保护端子的第二机翼上的第二导电端子，以及具有横臂的第一导电类型的电阻接触结构 与中心区域成一体，并且与第一导电端子欧姆接触的端部，电阻接触结构与第一机翼电绝缘。

公开(公告)号：US09407204B2

公开(公告)日：2016-08-02

申请号：US14219716

申请日：2014-03-19

Applicant: STMicroelectronics SA ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Vincent Heinrich ,  Bruno Paille

IPC: H04K1/10 ,  H04L27/28 ,  H03D3/06 ,  H04L27/144 ,  H04L27/16

CPC classification number: H03D3/06 ,  H04L27/144 ,  H04L27/16

Abstract: A method and corresponding device for processing a frequency-modulated analog signal are disclosed. The signal includes a number of symbols belonging to a set of M symbols respectively associated with at least one frequency of a set of M frequencies. The method includes a phase of reading each symbol of the signal that includes a sampling of a signal portion corresponding to the duration of a symbol and delivering N samples (M being less than N). M individual discrete Fourier transform processing operations are performed on the N samples. Each individual processing operation is associated with each of the frequencies. The M individual processing operations deliver M processing results. The value of the symbol can be determined from the M processing results.

Abstract translation: 公开了一种用于处理调频模拟信号的方法和相应装置。 信号包括属于一组M个符号的符号的数目，分别与一组M个频率的至少一个频率相关联。 该方法包括读取信号的每个符号的相位，其包括对应于符号的持续时间的信号部分的采样，并且递送N个采样（M小于N）。 对N个样本执行M个离散傅立叶变换处理操作。 每个单独的处理操作与每个频率相关联。 M个人处理操作提供M个处理结果。 可以从M处理结果确定符号的值。

公开(公告)号：US09405137B2

公开(公告)日：2016-08-02

申请号：US14283340

申请日：2014-05-21

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Robert Manouvrier

IPC: G02F1/025 ,  G02F1/225 ,  G02B6/12

CPC classification number: G02F1/025 ,  G02B6/12 ,  G02F1/2257 ,  H04B10/548

Abstract: A semiconductor electro-optical phase shifter may include an optical action zone configured to be inserted in an optical waveguide, and a bipolar transistor structure configured so that, in operation, collector current of the bipolar transistor structure crosses the optical action zone perpendicular to the axis of the optical waveguide.

公开(公告)号：US20160204031A1

公开(公告)日：2016-07-14

申请号：US15074130

申请日：2016-03-18

Applicant: STMicroelectronics SA

Inventor： Sylvain Joblot ,  Pierre Bar

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/66

CPC classification number: H01L21/76898 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01P3/003 ,  H01P3/006 ,  H01P11/003 ,  H01L2924/00

Abstract: In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line, including the steps of: forming active components and a set of front metallization levels; simultaneously etching from the rear surface of the substrate a through via hole and a trench crossing the substrate through at least 50% of its height; coating with a conductive material the walls and the bottom of the hole and of the trench; and filling the hole and the trench with an insulating filling material; and forming a coplanar line extending on the rear surface of the substrate, in front of the trench and parallel thereto, so that the lateral conductors of the coplanar line are electrically connected to the conductive material coating the walls of the trench.

公开(公告)号：US20160197048A1

公开(公告)日：2016-07-07

申请号：US15070046

申请日：2016-03-15

Applicant: STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Pierre Bar ,  Laurent Dussopt ,  Jean-Francois Carpentier

IPC: H01L23/66 ,  H01Q19/10 ,  H01L23/528 ,  H04B1/3827 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01Q13/10 ,  H01L23/522

CPC classification number: H01L23/66 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2924/15788 ,  H01Q1/243 ,  H01Q1/50 ,  H01Q9/0457 ,  H01Q13/106 ,  H01Q19/10 ,  H01Q23/00 ,  H04B1/3833 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04941

Abstract: A three-dimensional integrated structure includes a support element, an interface device connected to the support element by a first electrically conductive connection, and an integrated circuit arranged between the support element and the interface device and connected to the interface device by a second electrically conductive connection. A filler region is positioned between the second electrically conductive connection and between the interface device and the integrated circuit. An antenna is distributed over the interface device and the integrated circuit and has a radiating element electromagnetically coupled with an excitation element through the interconnection of a slot.

Abstract translation: 三维集成结构包括支撑元件，通过第一导电连接连接到支撑元件的接口装置，以及布置在支撑元件和接口装置之间并且通过第二导电连接到接口装置的集成电路 连接。 填充区域位于第二导电连接之间以及接口装置和集成电路之间。 天线分布在接口装置和集成电路上，并且具有通过插槽的互连与激励元件电磁耦合的辐射元件。

公开(公告)号：US20160173036A1

公开(公告)日：2016-06-16

申请号：US14955969

申请日：2015-12-01

Applicant: STMicroelectronics SA

Inventor： Lionel Vogt ,  Baudouin Martineau ,  Aurelien Larie

IPC: H03F1/02 ,  H03F3/193 ,  H03F3/21

CPC classification number: H03F1/0205 ,  H03F1/0261 ,  H03F3/193 ,  H03F3/195 ,  H03F3/211 ,  H03F3/245 ,  H03F3/45179 ,  H03F2200/432 ,  H03F2200/451 ,  H03F2200/516 ,  H03F2203/21106 ,  H03F2203/45394

Abstract: An amplifier includes at least two amplification stages coupled in parallel. Each amplification stage includes at differential pair of amplifying MOS transistors having gates connected to a first and second input nodes common to amplifying stages, and bulk regions connected to each other but insulated from bulk regions of the amplifying MOS transistors of the other amplification stages. A configuration circuit generates bias voltage for application to the bulk terminals in each amplification stage to set the threshold voltages of the amplifying MOS transistors, and thus configuring the operating range of each amplification stage so that different amplification stages have different operating ranges.

Abstract translation: 放大器包括并联耦合的至少两个放大级。 每个放大级包括在具有连接到放大级共同的第一和第二输入节点的栅极的差分对放大MOS晶体管和彼此连接但与其它放大级的放大MOS晶体管的体区绝缘的体区域。 配置电路产生用于施加到每个放大级中的批量端子的偏压，以设置放大MOS晶体管的阈值电压，从而构成每个放大级的工作范围，使得不同的放大级具有不同的工作范围。

公开(公告)号：US20160172404A1

公开(公告)日：2016-06-16

申请号：US14840665

申请日：2015-08-31

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (Crolles 2) SAS

Inventor： Nayera Ahmed ,  Michel Marty

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14683 ,  H01L27/14687 ,  H01L27/14689

Abstract: An image sensor including a semiconductor layer; a stack of insulating layers resting on the back side of the semiconductor layer; a conductive layer portion extending along part of the height of the stack and flush with the exposed surface of the stack; laterally-insulated conductive fingers extending through the semiconductor layer from its front side and penetrating into said layer portion; laterally-insulated conductive walls separating pixel areas, these walls extending through the semiconductor layer from its front side and having a lower height than the fingers; and an interconnection structure resting on the front side of the semiconductor layer and including vias in contact with the fingers.

Abstract translation: 包括半导体层的图像传感器; 沉积在半导体层的背面上的一叠绝缘层; 导电层部分，其沿所述堆叠的高度的一部分延伸并与所述堆叠的暴露表面齐平; 横向绝缘的导电指状物从其前侧延伸穿过半导体层并且穿透到所述层部分中; 分隔像素区域的横向绝缘导电壁，这些壁从其前侧延伸穿过半导体层并且具有比手指低的高度; 以及搁置在半导体层的前侧上并且包括与手指接触的通孔的互连结构。

公开(公告)号：US20160164493A1

公开(公告)日：2016-06-09

申请号：US14847900

申请日：2015-09-08

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Thomas Quemerais ,  Alice Bossuet ,  Daniel Gloria

IPC: H03H11/24 ,  G01R1/067 ,  H03F3/60

CPC classification number: H03H11/245 ,  G01R1/06711 ,  H03F3/602 ,  H03F2200/211

Abstract: An attenuator includes: a first circuit including a common collector or common drain amplifier formed of a first transistor having its control node connected to an input of the attenuator and its emitter or source connected to an intermediate node of the attenuator; and a second circuit including a common collector or common drain amplifier formed of a second transistor having its emitter or source connected to the intermediate node and its control node connected to an output of the attenuator.

Abstract translation: 衰减器包括：第一电路，包括由第一晶体管形成的公共集电极或公共放电放大器，第一晶体管的控制节点连接到衰减器的输入，其发射极或源极连接到衰减器的中间节点; 以及第二电路，包括由其第二晶体管形成的公共集电极或公共漏极放大器，其第二晶体管的发射极或源极连接到中间节点，其控制节点连接到衰减器的输出。

公开(公告)号：US09354391B2

公开(公告)日：2016-05-31

申请号：US14494647

申请日：2014-09-24

Applicant: STMicroelectronics SA

Inventor： Pascal Fonteneau

IPC: G02B6/12 ,  G02B6/122 ,  H01L25/16 ,  H01L27/02 ,  H01L23/60 ,  H01L25/065 ,  H01L23/00

CPC classification number: G02B6/4275 ,  G02B6/122 ,  G02B6/428 ,  G02B2006/12061 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/60 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/167 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/87 ,  H01L2224/16235 ,  H01L2225/06534 ,  H01L2225/06572 ,  H01L2924/10253 ,  H01L2924/1431

Abstract: A device includes integrated circuit chips mounted on one another. At least one component for protecting elements of a second chip is formed in a first chip. The chips may be of the SOI type, with the first chip including a first SOI layer having a first thickness and the second chip including a second SOI layer having a second thickness smaller than the first thickness. The first chip including the component for protecting may include an optical waveguide with the component for protecting formed adjacent the optical waveguide.

Abstract translation: 一种装置包括彼此安装的集成电路芯片。 用于保护第二芯片的元件的至少一个部件形成在第一芯片中。 芯片可以是SOI型，其中第一芯片包括具有第一厚度的第一SOI层，第二芯片包括第二厚度小于第一厚度的第二SOI层。 包括用于保护的部件的第一芯片可以包括具有邻近光波导形成的用于保护的部件的光波导。