公开(公告)号：US20130241025A1

公开(公告)日：2013-09-19

申请号：US13801354

申请日：2013-03-13

Applicant: STMICROELECTRONICS S.R.I.

Inventor： Alberto PAGANI

IPC: H01L27/02 ,  H01L21/768

CPC classification number: H01L27/0203 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L22/22 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49833 ,  H01L23/66 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/6677 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/02321 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/06187 ,  H01L2224/08137 ,  H01L2224/08146 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/14183 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/28105 ,  H01L2224/29024 ,  H01L2224/30183 ,  H01L2224/32145 ,  H01L2224/32227 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/48175 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73251 ,  H01L2224/82106 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06531 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15159 ,  H01L2924/207 ,  H05K1/181 ,  H05K1/189 ,  H05K2201/10515 ,  Y02P70/611 ,  H01L2224/02 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2224/32 ,  H01L2224/19 ,  H01L2924/00

Abstract: An embodiment of an electronic system may be provided so as to have superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in PCBs coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced.

Abstract translation: 可以提供电子系统的实施例，以便通过实现例如在系统中的有线和/或无线通信信道的基础上提供至少提供水平通信的通信机制来具有优异的耦合。 因此，通过增强电子系统中的垂直和水平通信能力，可以实现减小的总体尺寸，同时降低耦合到电子系统的PCB的复杂性。 以这种方式，可以提高复杂电子系统的总体制造成本和可靠性。

公开(公告)号：US20130159713A1

公开(公告)日：2013-06-20

申请号：US13735876

申请日：2013-01-07

Applicant: STMicroelectronics S.r.I. ,  Hewlett-Packard Development Company

Inventor： Liqun CHEN ,  Keith HARRISON ,  Guido Marco BERTONI ,  Pasqualina FRAGNETO ,  Gerardo PELOSI

IPC: H04L9/08

CPC classification number: H04L9/08 ,  H04L9/3073 ,  H04L9/321 ,  H04L2209/80 ,  H04W12/06

Abstract: An authentication method of a first module by a second module includes the steps of generating a first random datum by the second module to be sent to the first module, generating a first number by the first module starting from the first datum and by way of a private key, and generating a second number by the second module to be compared with the first number, so as to authenticate the first module. The step of generating the second number is performed starting from public parameters and is independent of the step of generating the first number.

Abstract translation: 通过第二模块的第一模块的认证方法包括以下步骤：由第二模块生成要发送到第一模块的第一随机数据，由第一模块从第一数据开始生成第一数字，并通过 私钥，并且由第二模块生成与第一号码进行比较的第二号码，以便认证第一模块。 从公共参数开始执行产生第二数量的步骤，并且独立于生成第一个数字的步骤。

公开(公告)号：US20130029486A1

公开(公告)日：2013-01-31

申请号：US13559433

申请日：2012-07-26

Applicant: Corrado Accardi ,  Stella Loverso ,  Sebastiano Ravesi ,  Noemi Graziana Sparta

Inventor： Corrado Accardi ,  Stella Loverso ,  Sebastiano Ravesi ,  Noemi Graziana Sparta

IPC: H01L21/768

CPC classification number: H01L21/6835 ,  H01L27/1266 ,  H01L51/003 ,  H01L51/0097 ,  H01L2221/6835 ,  H01L2227/326

Abstract: A method of manufacturing an electronic device on a plastic substrate includes: providing a carrier as a rigid support for the electronic device; providing a metallic layer on the carrier; forming the plastic substrate on the metallic layer, the metallic layer guaranteeing a temporary bonding of the plastic substrate to the carrier; forming the electronic device on the plastic substrate; and releasing the carrier from the plastic substrate. Releasing the carrier comprises immersing the electronic device bonded to the carrier in a oxygenated water solution that breaks the bonds between the plastic substrate and the metallic layer.

Abstract translation: 一种在塑料基板上制造电子装置的方法包括：提供作为电子设备的刚性支撑的载体; 在载体上提供金属层; 在金属层上形成塑料基板，金属层保证塑料基板临时粘合到载体上; 在塑料基板上形成电子器件; 并从塑料基板上释放载体。 释放载体包括将结合到载体上的电子装置浸入氧化水溶液中，破坏塑料基板和金属层之间的结合。

公开(公告)号：US20120329213A1

公开(公告)日：2012-12-27

申请号：US13533224

申请日：2012-06-26

Applicant: Vincenzo VINCIGUERRA ,  Luigi Giuseppe OCCHIPINTI

Inventor： Vincenzo VINCIGUERRA ,  Luigi Giuseppe OCCHIPINTI

IPC: H01L21/78

CPC classification number: H01L21/6835 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76259 ,  H01L22/00 ,  H01L22/14 ,  H01L23/49816 ,  H01L23/4985 ,  H01L23/5387 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/95 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/81001 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83851 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15788 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor device may have a thickness, such that the semiconductor devices are not flexible, and may be bonded and electrically coupled on a flexible substrate. After this bonding, the semiconductor device may be thinned so as to be rendered flexible.

Abstract translation: 半导体器件可以具有厚度，使得半导体器件不是柔性的，并且可以结合并电耦合在柔性衬底上。 在该接合之后，可以使半导体器件变薄以便变得柔性。

公开(公告)号：US20120308050A1

公开(公告)日：2012-12-06

申请号：US13484085

申请日：2012-05-30

Applicant: Edoardo Botti ,  Marco Zanettini ,  Matteo Bellitra

Inventor： Edoardo Botti ,  Marco Zanettini ,  Matteo Bellitra

IPC: H03G3/20 ,  H03F99/00

CPC classification number: H03F3/181 ,  H03F1/0211 ,  H03F3/72 ,  H03F2200/03 ,  H03F2200/393 ,  H03F2200/78 ,  H03F2203/7212 ,  H03G3/32 ,  H03G3/341 ,  H03G3/344

Abstract: The present invention concerns an audio amplifier circuit designed to provide an output signal to an audio transducer, said audio amplifier circuit comprising an audio power amplifier designed to receive an audio signal and designed to generate said output signal, a sensor designed to detect an audible sound having at least one noise component, to generate a detected signal. The audio amplifier circuit also includes a processing block configured to receive said detected signal at its input and to generate an off signal at its output, the latter being located at the input of said audio power amplifier. The processing block processes the detected signal according to said input signal to identify said noise component of said detected signal to generate a reference signal. The processing block generates the off signal when the value of said input signal is lower than the value of said reference signal.

Abstract translation: 本发明涉及一种设计用于向音频传感器提供输出信号的音频放大器电路，所述音频放大器电路包括设计用于接收音频信号并被设计为产生所述输出信号的音频功率放大器，设计用于检测可听见的声音的传感器 具有至少一个噪声分量，以产生检测信号。 音频放大器电路还包括处理块，其被配置为在其输入处接收所述检测到的信号，并在其输出端产生关闭信号，后者位于所述音频功率放大器的输入端。 处理块根据所述输入信号处理所检测的信号，以识别所述检测信号的所述噪声分量以产生参考信号。 当所述输入信号的值低于所述参考信号的值时，处理块产生关闭信号。

公开(公告)号：US20120268186A1

公开(公告)日：2012-10-25

申请号：US13538802

申请日：2012-06-29

Applicant: Sandro Rossi ,  Giulio Ricotti

Inventor： Sandro Rossi ,  Giulio Ricotti

IPC: H03K5/08

CPC classification number: G05F3/02 ,  H03K19/018521 ,  H03K19/09443

Abstract: A transmission channel includes at least one high voltage buffer block having buffer transistors and respective buffer diodes, being electrically coupled between respective voltage reference terminals, these buffer transistors being also coupled to a clamping block, in turn including clamping transistors connected to at least one output terminal of this transmission channel through diodes coupled to prevent the body diodes of the clamping transistors from conducting. The transmission channel includes at least one reset circuit having diodes and being electrically coupled between circuit nodes of the high voltage buffer block and of the clamping block, these circuit nodes being in correspondence with conduction terminals of the transistors comprised into the high voltage buffer block and into the clamping block.

Abstract translation: 传输通道包括至少一个具有缓冲晶体管和相应的缓冲二极管的高电压缓冲器块，其电耦合在相应的电压参考端子之间，这些缓冲晶体管还耦合到钳位块，反过来还包括连接到至少一个输出端的钳位晶体管 该传输通道的端子通过二极管耦合以防止钳位晶体管的体二极管导通。 传输通道包括至少一个具有二极管的复位电路，并且电耦合在高电压缓冲块和钳位块的电路节点之间，这些电路节点对应于包含在高电压缓冲块中的晶体管的导电端子， 进入夹紧块。

公开(公告)号：US20120261720A1

公开(公告)日：2012-10-18

申请号：US13441640

申请日：2012-04-06

Applicant: Valeria Puglisi ,  Corinna Altamore ,  Giovanni Abagnale

Inventor： Valeria Puglisi ,  Corinna Altamore ,  Giovanni Abagnale

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462

Abstract: A method for manufacturing a HEMT transistor includes: realizing an undoped epitaxial layer on a substrate; realizing a barrier epitaxial layer on the undoped epitaxial layer so as to form a heterojunction; realizing source and drain structures, separated from one other, on the barrier epitaxial layer; depositing an insulating layer on the barrier epitaxial layer and on the source and drain structures; and photolithographic defining the insulating layer, defining first and second insulating portions in correspondence of the source and drain structures, respectively, and exposing a portion of the barrier epitaxial layer. The method further comprises: forming first and second spacers lying at the corners of the first and second insulating portions; and depositing a gate metal structure at least partially covering said first and second insulating portions, and said first and second spacers, said gate metal structure being a field plate of the HEMT transistor.

Abstract translation: 一种制造HEMT晶体管的方法包括：在衬底上实现未掺杂的外延层; 在未掺杂的外延层上实现阻挡外延层以形成异质结; 实现在隔离外延层上彼此分离的源极和漏极结构; 在阻挡层外延层和源极和漏极结构上沉积绝缘层; 和光刻法，限定绝缘层，分别对应于源极和漏极结构限定第一和第二绝缘部分，并暴露出阻挡外延层的一部分。 该方法还包括：形成位于第一和第二绝缘部分的角部的第一和第二间隔物; 以及沉积栅极金属结构，至少部分地覆盖所述第一和第二绝缘部分，以及所述第一和第二间隔物，所述栅极金属结构是所述HEMT晶体管的场板。

公开(公告)号：US20120248347A1

公开(公告)日：2012-10-04

申请号：US13431831

申请日：2012-03-27

Applicant: Lucio Renna ,  Clelia Galati ,  Piero Giorgio Fallica

Inventor： Lucio Renna ,  Clelia Galati ,  Piero Giorgio Fallica

IPC: G01N21/01 ,  B29D11/00 ,  G01J1/42

CPC classification number: G02B21/0032 ,  G01J1/0266 ,  G01J1/0411 ,  G01J1/0437 ,  G01J1/0488 ,  G01J1/44 ,  G01N21/6452

Abstract: A confocal optical detector including a light source generating a first optical beam along an axis; an optoelectronic sensor; an optical focusing device, which receives and focuses the first optical beam; and a hole, which receives the first optical beam and is arranged between the optoelectronic sensor and the optical focusing device. The optoelectronic sensor is arranged between the light source and the hole. In addition, the optoelectronic sensor and the optical focusing device are aligned along the axis.

Abstract translation: 一种共焦光学检测器，包括沿轴线产生第一光束的光源; 光电传感器; 光聚焦装置，其接收和聚焦第一光束; 以及孔，其接收第一光束并且布置在光电传感器和光聚焦装置之间。 光电传感器布置在光源和孔之间。 此外，光电传感器和光学聚焦装置沿轴线对准。

公开(公告)号：US20120221827A1

公开(公告)日：2012-08-30

申请号：US13406186

申请日：2012-02-27

Applicant: Maurizio Francesco Perroni ,  Giuseppe Castagna

Inventor： Maurizio Francesco Perroni ,  Giuseppe Castagna

IPC: G06F12/06

CPC classification number: G11C16/08

Abstract: An address decoding device may include a supply terminal for a supply voltage, a conductive path configured to provide an electric signal, associated with an address of at least one memory cell, and an address terminal connected to the conductive path and structured to receive the electric signal. An address decoder may be connected to the address terminal to receive the electric signal. The decoder may have a decoding operative voltage associated therewith. A switch circuit may be structured to electrically connect the address terminal to the supply terminal when the address terminal takes a threshold voltage imposed by the electric signal, and may bring the address terminal to the decoding operative voltage.

Abstract translation: 地址解码装置可以包括用于电源电压的供电端子，被配置为提供与至少一个存储单元的地址相关联的电信号的导电路径，以及连接到导电路径并被构造为接收电 信号。 地址解码器可以连接到地址终端以接收电信号。 解码器可以具有与其相关联的解码操作电压。 当地址端子接收到电信号施加的阈值电压时，开关电路可以被构造为将地址端子电连接到电源端子，并且可以将地址端子带到解码操作电压。

公开(公告)号：US20120220090A1

公开(公告)日：2012-08-30

申请号：US13409411

申请日：2012-03-01

Applicant: Angelo MAGRI ,  Antonino Sebastiano ALESSANDRIA ,  Stefania FORTUNA ,  Leonardo FRAGAPANE

Inventor： Angelo MAGRI ,  Antonino Sebastiano ALESSANDRIA ,  Stefania FORTUNA ,  Leonardo FRAGAPANE

IPC: H01L21/336 ,  H01L21/283

CPC classification number: H01L29/1037 ,  H01L29/405 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: An embodiment of a method for manufacturing a power device being integrated on a semiconductor substrate comprising at least the steps of making, in the semiconductor substrate, at least a trench having sidewalls and a bottom, covering the sidewalls and the bottom of said at least one trench with a first insulating coating layer and making, inside said at least one trench, a conductive gate structure. An embodiment of the method provides the formation of the conductive gate structure comprising the steps of covering at least the sidewalls with a second conductive coating layer of a first conductive material; making a conductive central region of a second conductive material having a different resistivity than the first conductive material; and making a plurality of conductive bridges between said second conductive coating layer and said conductive central region.

Abstract translation: 一种用于制造集成在半导体衬底上的功率器件的方法的实施例，至少包括以下步骤：在半导体衬底中至少形成具有侧壁和底部的沟槽，覆盖所述至少一个的侧壁和底部 沟槽，其具有第一绝缘涂层并且在所述至少一个沟槽内部形成导电栅极结构。 该方法的一个实施例提供了导电栅极结构的形成，包括以下步骤：用第一导电材料的第二导电涂层覆盖至少侧壁; 制造具有与第一导电材料不同的电阻率的第二导电材料的导电中心区域; 以及在所述第二导电涂层和所述导电中心区之间形成多个导电桥。