公开(公告)号：US20110259627A1

公开(公告)日：2011-10-27

申请号：US13067883

申请日：2011-07-01

Applicant: Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

IPC: H05K1/09 ,  H05K1/11

CPC classification number: H05K3/205 ,  H01L21/4846 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K3/4007 ,  H05K2201/09745 ,  H05K2201/10674 ,  H05K2203/0338 ,  H05K2203/0435 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit board includes: an insulator having a groove; a circuit layer filling a portion of the groove; a solder pad on the circuit layer filling the remainder of the groove; and a circuit pattern electrically connected with the circuit layer, the circuit pattern buried in the insulator such that a portion of the circuit pattern is exposed at a surface of the insulator.

Abstract translation: 电路板包括：具有凹槽的绝缘体; 填充所述凹槽的一部分的电路层; 电路层上的填充凹槽其余部分的焊盘; 以及与电路层电连接的电路图案，电路图案埋在绝缘体中，使得电路图案的一部分在绝缘体的表面露出。

公开(公告)号：US07550316B2

公开(公告)日：2009-06-23

申请号：US11715906

申请日：2007-03-09

Applicant: Myung-Sam Kang ,  Chang-Sup Ryu ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

Inventor： Myung-Sam Kang ,  Chang-Sup Ryu ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/3128 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An aspect of the present invention features a manufacturing method of a board on chip package. The method can comprise: (a) laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; (b) patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and a circuit wire; (c) removing the dry film; (d) laminating an upper photo solder resist excluding a portion where the solder ball pad is formed; (e) etching the thin metal film formed on a portion where the upper photo solder resist is not laminated; (f) mounting a semiconductor chip on the solder ball pad by a flip chip bonding; (g) molding the semiconductor chip with a passivation material; (h) removing the carrier film and the thin metal film; and (i) laminating a lower photo solder resist under the solder ball pad. The board on chip package and the manufacturing method thereof according to the present invention can design a high density circuit since a circuit pattern is formed using a seed layer.

Abstract translation: 本发明的一个方面的特征在于片上封装的制造方法。 该方法可以包括：（a）在载体膜上层压干膜，其一面由薄金属膜层压; （b）通过曝光和显影工艺根据电路线图案化干膜，并形成焊球焊盘和电路线; （c）去除干膜; （d）层压除了形成焊锡球焊盘的部分之外的上光阻焊剂; （e）蚀刻形成在上层光阻抗层未层叠的部分上的金属薄膜; （f）通过倒装芯片接合将半导体芯片安装在焊球垫上; （g）用钝化材料模制半导体芯片; （h）去除载体膜和金属薄膜; 和（i）在焊球垫下方层叠下光阻焊剂。 根据本发明的片上封装及其制造方法可以设计高密度电路，因为使用种子层形成电路图案。

公开(公告)号：US20080101045A1

公开(公告)日：2008-05-01

申请号：US11976070

申请日：2007-10-19

Applicant: Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

IPC: H05K1/18 ,  H05K3/20

CPC classification number: H05K3/205 ,  H01L21/4846 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K3/4007 ,  H05K2201/09745 ,  H05K2201/10674 ,  H05K2203/0338 ,  H05K2203/0435 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of manufacturing a circuit board, which includes a bump pad on which a solder bump may be placed, may include forming a solder pad on a surface of a first carrier; forming a metal film, which covers the solder pad and which extends to a bump pad forming region; forming a circuit layer and a circuit pattern, which are electrically connected with the metal film, on a surface of the first carrier; pressing the first carrier and an insulator such that a surface of the first carrier and the insulator faces each other; and removing the first carrier. Utilizing this method, the amount of solder for the contacting of a flip chip can be adjusted, and solder can be filled inside the board, so that after installing a chip, the overall thickness of the package can be reduced.

Abstract translation: 一种制造电路板的方法，包括可以放置焊锡凸块的凸块焊盘，可以包括在第一载体的表面上形成焊盘; 形成覆盖焊盘并延伸到凸块焊盘形成区域的金属膜; 在所述第一载体的表面上形成与所述金属膜电连接的电路层和电路图案; 按压所述第一载体和绝缘体，使得所述第一载体和所述绝缘体的表面彼此面对; 并移除第一载体。 利用这种方法，可以调节用于接合倒装芯片的焊料的量，并且可以在板内填充焊料，使得在安装芯片之后，可以减小封装的整体厚度。

公开(公告)号：US20080006942A1

公开(公告)日：2008-01-10

申请号：US11708568

申请日：2007-02-21

Applicant: Jung-Hyun Park ,  Byoung-Youl Min ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Hoe-Ku Jung ,  Ji-Eun Kim

Inventor： Jung-Hyun Park ,  Byoung-Youl Min ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Hoe-Ku Jung ,  Ji-Eun Kim

IPC: H01L23/52 ,  H01L21/00

CPC classification number: H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A bottom substrate of package on package and manufacturing method thereof is disclosed. A bottom substrate of a package on package electrically connected to a top substrate by means of a solder ball, including a core board, a solder ball pad formed on a surface of the core board in correspondence with a location of the solder ball, an insulation layer laminated on the core board, a through hole formed by removing a part of the insulation layer such that the solder ball pad is exposed, and a metallic layer filled in the through hole and connected electrically with the solder ball, allows the number of ICs mounted on a bottom substrate to be increased without increasing the size of a solder ball, and allows the size and pitch of the solder balls to be made smaller by controlling the thickness of the insulation layer laminated on the bottom substrate, whereby more signal transmission is possible between a top substrate and a bottom substrate.

Abstract translation: 公开了一种封装的底部衬底及其制造方法。 封装的封装的底部衬底通过焊球电连接到顶部衬底，所述焊球包括芯板，与所述焊球的位置对应地形成在所述芯板的表面上的焊球焊盘，绝缘体 层叠在芯板上的通孔，通过去除绝缘层的一部分使得焊球焊盘露出而形成的通孔以及填充在通孔中并与焊球电连接的金属层允许IC的数量 安装在底部基板上以增加焊球的尺寸，并且通过控制层叠在底部基板上的绝缘层的厚度，可以使焊球的尺寸和间距变小，由此更多的信号传输是 可能在顶部基板和底部基板之间。

公开(公告)号：US20070281390A1

公开(公告)日：2007-12-06

申请号：US11727852

申请日：2007-03-28

Applicant: Myung-Sam Kang ,  Je-Gwang Yoo ,  Jung-Hyun Park ,  Ji-Eun Kim ,  Hoe-Ku Jung ,  Jin-Yong An

Inventor： Myung-Sam Kang ,  Je-Gwang Yoo ,  Jung-Hyun Park ,  Ji-Eun Kim ,  Hoe-Ku Jung ,  Jin-Yong An

IPC: H01L21/00

CPC classification number: H01L21/4846 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/064 ,  H05K3/108 ,  H05K3/242 ,  H05K3/243 ,  H05K3/427 ,  H05K2201/0376 ,  H05K2203/0361 ,  H05K2203/1394 ,  H01L2924/00

Abstract: The present invention relates to a manufacturing method of a package substrate. A manufacturing method of a package substrate for mounting an electric component by connecting electrodes of the electric component to bonding pads, includes: manufacturing a buried pattern substrate having a circuit pattern and bonding pads buried in an insulating layer and having a seed layer laminated on the insulating layer, laminating a dry film onto the seed layer and removing the seed layer and the dry film of the upper side of the bonding pads, performing surface-treatment using the remaining seed layer as a plating lead; and removing the remaining seed layer and the dry film such that the circuit pattern is exposed.

Abstract translation: 本发明涉及封装基板的制造方法。 一种用于通过将电气部件的电极连接到接合焊盘来安装电气部件的封装基板的制造方法，包括：制造具有电路图案的掩埋图案基板和埋在绝缘层中并具有层叠在所述绝缘层上的种子层的接合焊盘 绝缘层，将干膜层压到种子层上，去除接合焊盘的上侧的种子层和干膜，使用剩余的种子层作为电镀引线进行表面处理; 并且除去剩余的种子层和干膜，使得电路图案被暴露。

公开(公告)号：US20070210439A1

公开(公告)日：2007-09-13

申请号：US11715906

申请日：2007-03-09

Applicant: Myung-Sam Kang ,  Chang-Sup Ryu ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

Inventor： Myung-Sam Kang ,  Chang-Sup Ryu ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/3128 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An aspect of the present invention features a manufacturing method of a board on chip package. The method can comprise: (a) laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; (b) patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and a circuit wire; (c) removing the dry film; (d) laminating an upper photo solder resist excluding a portion where the solder ball pad is formed; (e) etching the thin metal film formed on a portion where the upper photo solder resist is not laminated; (f) mounting a semiconductor chip on the solder ball pad by a flip chip bonding; (g) molding the semiconductor chip with a passivation material; (h) removing the carrier film and the thin metal film; and (i) laminating a lower photo solder resist under the solder ball pad. The board on chip package and the manufacturing method thereof according to the present invention can design a high density circuit since a circuit pattern is formed using a seed layer.

Abstract translation: 本发明的一个方面的特征在于片上封装的制造方法。 该方法可以包括：（a）在载体膜上层压干膜，其一面由薄金属膜层压; （b）通过曝光和显影工艺根据电路线图案化干膜，并形成焊球焊盘和电路线; （c）去除干膜; （d）层压除了形成焊锡球焊盘的部分之外的上光阻焊剂; （e）蚀刻形成在上层光阻抗层未层叠的部分上的金属薄膜; （f）通过倒装芯片接合将半导体芯片安装在焊球垫上; （g）用钝化材料模制半导体芯片; （h）去除载体膜和金属薄膜; 和（i）在焊球垫下方层叠下光阻焊剂。 根据本发明的片上封装及其制造方法可以设计高密度电路，因为使用种子层形成电路图案。

公开(公告)号：US08418355B2

公开(公告)日：2013-04-16

申请号：US11976071

申请日：2007-10-19

Applicant: Sang-Duck Kim ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jong-Gyu Choi ,  Ji-Eun Kim ,  Jeong-Woo Park

Inventor： Sang-Duck Kim ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jong-Gyu Choi ,  Ji-Eun Kim ,  Jeong-Woo Park

IPC: H05K3/20

CPC classification number: H05K3/20 ,  H05K3/205 ,  H05K3/207 ,  H05K3/386 ,  H05K2203/0113 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49163

Abstract: A method for forming transcriptional circuits and a method for manufacturing a circuit board are disclosed. A method of forming a transcriptional circuit, which includes forming an intaglio pattern corresponding to a circuit pattern by selectively forming a resist on a mold board, filling conductive material in the intaglio pattern, and transferring the conductive material onto a carrier by pressing the carrier onto the mold board such that the carrier faces the surface of the mold board having the conductive material filled in, makes it possible to form transcriptional circuits that can be transcribed into an insulation board using existing equipment, whereby costs can be reduced.

Abstract translation: 公开了一种形成转录电路的方法及其制造方法。 一种形成转录电路的方法，其包括通过在模板上选择性地形成抗蚀剂来形成对应于电路图案的凹版图案，将导电材料填充到凹版图案中，以及通过将载体压载到载体上而将载体转移到 使得载体面向具有填充有导电材料的模板的表面的模板，使得可以形成可以使用现有设备转录成绝缘板的转录电路，由此可以降低成本。

公开(公告)号：US08003439B2

公开(公告)日：2011-08-23

申请号：US12385316

申请日：2009-04-03

Applicant: Myung-Sam Kang ,  Chang-Sup Ryu ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

Inventor： Myung-Sam Kang ,  Chang-Sup Ryu ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

IPC: H01L21/00

CPC classification number: H01L23/3128 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacturing a board on chip package including laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and a circuit wire; removing the dry film; laminating an upper photo solder resist excluding a portion where the solder ball pad is formed; etching the thin metal film formed on a portion where the upper photo solder resist is not laminated; mounting a semiconductor chip on the solder ball pad by a flip chip bonding; molding the semiconductor chip with a passivation material; removing the carrier film and the thin metal film; and laminating a lower photo solder resist under the solder ball pad. The board on chip package provides a high density circuit since a circuit pattern is formed using a seed layer.

Abstract translation: 一种制造片上封装的方法，包括在载体膜上层叠干膜，其一面由薄金属膜层压; 通过曝光和显影工艺根据电路线图案化干膜，并形成焊球焊盘和电路线; 去除干膜; 层压除了形成焊球垫的部分之外的上光阻焊剂; 蚀刻形成在上层光阻焊层未层叠的部分上的金属薄膜; 通过倒装芯片焊接将半导体芯片安装在焊球垫上; 用钝化材料成型半导体芯片; 去除载体膜和金属薄膜; 并在焊球下方层叠下光阻焊剂。 由于使用种子层形成电路图案，片上封装芯片提供了高密度电路。

公开(公告)号：US07937833B2

公开(公告)日：2011-05-10

申请号：US11976072

申请日：2007-10-19

Applicant: Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

IPC: H03K3/02

CPC classification number: H05K3/20 ,  H05K3/0058 ,  H05K3/108 ,  H05K3/4611 ,  H05K3/4682 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2203/0152 ,  H05K2203/0376 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A method of manufacturing a circuit board is disclosed. A method of manufacturing a circuit board that includes forming a first circuit pattern on the insulation layer of a carrier, in which an insulation layer and a first seed layer are stacked in order; stacking and pressing the carrier and an insulation board with the side of the carrier having the first circuit pattern facing the insulation board; removing the carrier to transfer the first circuit pattern and the insulation layer onto the insulation board; and forming a second circuit pattern on the insulation layer transferred to the insulation board, allows fine pitch circuit patterns to enable the manufacture of fine circuit patterns of high density on the board, and allows the manufacture of a multi-layer circuit board with a simple process.

Abstract translation: 公开了一种制造电路板的方法。 一种制造电路板的方法，包括在载体的绝缘层上形成第一电路图案，其中绝缘层和第一种子层依次层叠; 堆叠并按压载体和绝缘板，其中载体侧具有面向绝缘板的第一电路图案; 移除载体以将第一电路图案和绝缘层转移到绝缘板上; 并且在转移到绝缘板的绝缘层上形成第二电路图案，允许精细的间距电路图案能够在板上制造高密度的精细电路图案，并且允许制造具有简单的多层电路板 处理。

公开(公告)号：US07858437B2

公开(公告)日：2010-12-28

申请号：US11706186

申请日：2007-02-15

Applicant: Hoe-Ku Jung ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jung-Hyun Park

IPC: H01L21/44

CPC classification number: H01L21/481 ,  H01L23/13 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1058 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/183 ,  H05K3/205 ,  H05K3/4658 ,  H05K3/4697 ,  H05K2203/0568 ,  H05K2203/0571 ,  H05K2203/308 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An aspect of the present invention features a method for manufacturing a substrate having a cavity. The method can comprises: (a) forming an upper layer circuit on an upper seed layer; (b) laminating a dry film on a portion of the upper seed layer where a cavity is to be formed; (c) fabricating an upper outer layer by forming an insulation layer on top of the upper seed layer and on top and sides of the upper layer circuit; (d) stacking the upper outer layer on one side of a core layer where an internal circuit is formed; (e) removing the upper seed layer; and (f) forming the cavity by removing the dry film. The method for manufacturing a substrate with a cavity according to the present invention can reduce the total thickness of the substrate while the thickness of an insulation layer remains the same, by forming the insulation layer on sides of an external circuit.

Abstract translation: 本发明的一个方面的特征在于一种用于制造具有腔的衬底的方法。 该方法可以包括：（a）在上部种子层上形成上层电路; （b）在要形成空腔的上种子层的一部分上层压干膜; （c）通过在上部种子层的顶部和上层电路的顶部和侧面上形成绝缘层来制造上部外层; （d）在形成有内部电路的芯层的一侧堆叠上外层; （e）去除上部种子层; 和（f）通过去除干膜形成空腔。 根据本发明的用于制造具有腔的衬底的方法可以通过在外部电路的侧面上形成绝缘层来减小衬底的总厚度，同时绝缘层的厚度保持相同。