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    Assembly Method For Reworkable Chip Stacking With Conductive Film
    21.
    发明申请
    Assembly Method For Reworkable Chip Stacking With Conductive Film 审中-公开
    带导电膜的可重复芯片堆叠的装配方法

    公开(公告)号：US20090181476A1

    公开(公告)日：2009-07-16

    申请号：US11972129

    申请日：2008-01-10

    Applicant: Stephen L. Buchwalter ,  Bing Dang ,  Claudius Feger ,  Peter A. Gruber ,  John Knickerbocker

    Inventor： Stephen L. Buchwalter ,  Bing Dang ,  Claudius Feger ,  Peter A. Gruber ,  John Knickerbocker

    IPC: H01L21/02

    CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of stacking a chip, including an integrated circuit, onto a substrate including applying an anisotropic conductive film (ACF) or a solder-filled conductive film onto a surface thereof, the surface being configured to electrically couple to the film, placing the chip onto the film, the chip being configured to electrically couple to the film, compressively pressurizing the chip, the film and the surface such that the chip is electrically coupled to the surface via the film,, testing the chip to determine whether the chip is operating normally, reworking the placement of the chip onto the film and repeating the compressive pressurization if the chip is determined to not be operating normally, repeating the testing to determine whether the chip is operating normally, and once the chip is determined to be operating normally, bonding the chip, the film and the surface.

    Abstract translation: 一种将包括集成电路的芯片堆叠在基板上的方法，包括将各向异性导电膜（ACF）或焊料填充导电膜施加到其表面上，该表面被配置为电耦合到膜，将芯片 芯片被配置为电耦合到膜，对芯片，膜和表面进行压缩加压，使得芯片经由膜电耦合到表面，测试芯片以确定芯片是否正在操作 通常，如果芯片被确定为不正常工作，重复测试以确定芯片是否正常工作，并且一旦芯片确定正常工作，则将芯片放置在膜上并重复压缩加压， 粘合芯片，薄膜和表面。

    Method and structure for two-dimensional optical fiber ferrule
    23.
    发明申请
    Method and structure for two-dimensional optical fiber ferrule 失效
    二维光纤套圈的方法和结构

    公开(公告)号：US20050152650A1

    公开(公告)日：2005-07-14

    申请号：US10756782

    申请日：2004-01-13

    Applicant: John Knickerbocker ,  How Lin

    Inventor： John Knickerbocker ,  How Lin

    IPC: G02B6/36 ,  G02B6/38

    CPC classification number: G02B6/3672 ,  G02B6/3644 ,  G02B6/3692 ,  G02B6/3696 ,  G02B6/3885

    Abstract: A method is provided for making ferrules for connecting optical fibers to other optical fibers or to an optical input device such as an optical chip. The method utilizes ceramic greensheets or silicon wafers. In one method, the greensheets are stacked and laminated and then fiber optic through openings are provided in the laminate for holding the fibers. The laminate is then sintered forming the ferrule.

    Abstract translation: 提供了一种用于制造用于将光纤连接到其它光纤或光输入装置（例如光学芯片）的套圈的方法。 该方法采用陶瓷片或硅片。 在一种方法中，将绿色纸堆叠并层压，然后在用于保持纤维的层压体中设置光纤通孔。 然后将层压体烧结形成套圈。

    Laser Ablation for Integrated Circuit Fabrication
    25.
    发明申请
    Laser Ablation for Integrated Circuit Fabrication 有权
    激光消融用于集成电路制造

    公开(公告)号：US20110290406A1

    公开(公告)日：2011-12-01

    申请号：US12788843

    申请日：2010-05-27

    Applicant: Bing Dang ,  John Knickerbocker ,  Aparna Prabhakar ,  Peter Sorce ,  Robert E. Trzcinski ,  Cornelia K. Tsang

    Inventor： Bing Dang ,  John Knickerbocker ,  Aparna Prabhakar ,  Peter Sorce ,  Robert E. Trzcinski ,  Cornelia K. Tsang

    IPC: B29C65/16

    CPC classification number: H01L21/6835 ,  B23K26/361 ,  H01L2221/68381 ,  Y10T156/1111 ,  Y10T156/1158 ,  Y10T156/1917

    Abstract: A method for releasing a handler from a wafer, the wafer comprising an integrated circuit (IC) includes attaching the handler to the wafer using an adhesive comprising a polymer; performing edge processing to remove an excess portion of the adhesive from an edge of the handler and wafer; ablating the adhesive through the handler using a laser, wherein a wavelength of the laser is selected based on the transparency of the handler material; and separating the handler from the wafer. A system for releasing a handler from a wafer, the wafer comprising an IC includes a handler attached to a wafer using an adhesive comprising a polymer; an edge processing module, the edge processing module configured to remove an excess portion of the adhesive from the edge of the handler and wafer; and a laser, the laser configured to ablate the adhesive through the handler.

    Abstract translation: 一种用于从晶片释放处理器的方法，包括集成电路（IC）的晶片包括使用包含聚合物的粘合剂将处理器附接到晶片; 执行边缘处理以从处理器和晶片的边缘去除多余的粘合剂部分; 使用激光器通过处理器烧蚀粘合剂，其中基于处理材料的透明度选择激光的波长; 并将处理器与晶片分离。 一种用于从晶片释放处理器的系统，包括IC的晶片包括使用包含聚合物的粘合剂连接到晶片的处理器; 边缘处理模块，所述边缘处理模块被配置为从所述处理器和晶片的边缘去除所述粘合剂的多余部分; 和激光器，激光器被配置为通过处理器消融粘合剂。

    Rotational fill techniques for injection molding of solder
    28.
    发明申请
    Rotational fill techniques for injection molding of solder 失效
    用于注射成型焊料的旋转填充技术

    公开(公告)号：US20070246515A1

    公开(公告)日：2007-10-25

    申请号：US11409232

    申请日：2006-04-21

    Applicant: Steven Cordes ,  Peter Gruber ,  John Knickerbocker ,  James Speidell

    Inventor： Steven Cordes ,  Peter Gruber ,  John Knickerbocker ,  James Speidell

    IPC: B23K31/02 ,  B23K1/08 ,  B23K35/12

    CPC classification number: B23K3/0638 ,  B23K35/02 ,  B23K2101/40 ,  H01L2224/11

    Abstract: A system and method for injection molding conductive bonding material into a plurality of cavities in a non-rectangular mold is disclosed. The method comprises aligning a fill head with a non-rectangular mold. The non-rectangular mold includes a plurality of cavities. The fill head is placed in substantial contact with the non-rectangular mold. Rotational motion is provided to at least one of the non-rectangular mold and the fill head while the fill head is in substantial contact with the non-rectangular mold. Conductive bonding material is forced out of the fill head toward the non-rectangular mold. The conductive bonding material is provided into at least one cavity of the plurality of cavities contemporaneous with the at least one cavity being in proximity to the fill head.

    Abstract translation: 公开了一种用于将导电接合材料注射成非矩形模具中的多个空腔的系统和方法。 该方法包括将填充头与非矩形模具对准。 非矩形模具包括多个空腔。 填充头被放置成与非矩形模具基本接触。 旋转运动提供给非矩形模具和填充头中的至少一个，同时填充头基本上与非矩形模具接触。 将导电接合材料从填充头推向非矩形模具。 导电接合材料被提供到与填充头附近的至少一个空腔同时的多个空腔的至少一个空腔中。

    Techniques for providing decoupling capacitance
    29.
    发明申请
    Techniques for providing decoupling capacitance 失效
    提供去耦电容的技术

    公开(公告)号：US20070035030A1

    公开(公告)日：2007-02-15

    申请号：US11201572

    申请日：2005-08-11

    Applicant: Raymond Horton ,  John Knickerbocker ,  Edmund Sprogis ,  Cornelia Tsang

    Inventor： Raymond Horton ,  John Knickerbocker ,  Edmund Sprogis ,  Cornelia Tsang

    IPC: H01L23/48

    CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5382 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311

    Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

    Abstract translation: 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。

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