公开(公告)号：US20160260769A1

公开(公告)日：2016-09-08

申请号：US15153702

申请日：2016-05-12

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： TSENG-FEI WEN

IPC: H01L27/146

CPC classification number: H01L27/14685 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14689 ,  H01L27/14698 ,  H01L31/0232 ,  H01L31/02327 ,  H01L31/18

Abstract: A fabricating method of a back-illuminated image sensor includes the following steps. First, a silicon wafer having a first surface and a second surface is provided, wherein a number of trench isolations are formed in the first surface, and at least one image sensing member is formed between the trench isolations. Then, a first chemical mechanical polishing (CMP) process is performed to the second surface using the trench isolations as a polishing stop layer to thin the silicon wafer. Because the polishing rate of the silicon material in the silicon wafer is different with that of the isolation material of the trench isolations in the first CMP process, at least one dishing depression is formed in the second surface of the silicon wafer. Finally, a microlens is formed above the dishing depression, and a surface of the microlens facing the dishing depression is a curved surface.

Abstract translation: 背照式图像传感器的制造方法包括以下步骤。 首先，提供具有第一表面和第二表面的硅晶片，其中在第一表面中形成多个沟槽隔离，并且在沟槽隔离件之间形成至少一个图像感测构件。 然后，使用沟槽隔离作为抛光停止层对第二表面进行第一化学机械抛光（CMP）处理以使硅晶片变薄。 由于硅晶片中的硅材料的抛光速率与第一CMP工艺中的沟槽隔离物的隔离材料的抛光速率不同，所以在硅晶片的第二表面中形成至少一个凹陷凹陷。 最后，在凹陷凹陷之上形成微透镜，并且面对凹陷凹陷的微透镜的表面是曲面。

公开(公告)号：US09411240B2

公开(公告)日：2016-08-09

申请号：US14277788

申请日：2014-05-15

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Zhong-Gui Zhang

IPC: G03F7/20

CPC classification number: G03F7/70066 ,  G03F7/20 ,  G03F7/70083 ,  G03F7/70558

Abstract: A method for compensating a slit illumination uniformity includes executing a first lithography operation and recording an initial slit uniformity profile; executing a slit uniformity optimization process and recording an optimized slit uniformity profile; and offsetting the optimized slit uniformity profile to obtain a working slit uniformity profile such that the working slit uniformity profile has a mean value closest to that of the initial slit uniformity profile.

Abstract translation: 用于补偿狭缝照射均匀性的方法包括执行第一光刻操作并记录初始狭缝均匀性轮廓; 执行狭缝均匀性优化处理并记录优化的狭缝均匀性轮廓; 并且抵消优化的狭缝均匀度轮廓以获得工作狭缝均匀性轮廓，使得工作狭缝均匀性轮廓具有最接近初始狭缝均匀性轮廓的平均值。

公开(公告)号：US09379182B1

公开(公告)日：2016-06-28

申请号：US14612352

申请日：2015-02-03

Applicant: United Microelectronics Corporation

Inventor： Chun Jen Chen ,  Bin-Siang Tsai ,  Tsai-Yu Wen ,  Yu Shu Lin ,  Chin-Sheng Yang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02 ,  H01L29/423 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02587 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/76224 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/16 ,  H01L29/165 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method for forming germanium nanowires comprises forming a semiconductor fin structure including alternating fin and shallow trench structures, etching a top portion of the fin to form a fin recess and depositing a germanium-based semiconductor into the fin recess as a germanium-based plug. The method comprises etching the shallow trench structure to expose the germanium-based semiconductor side faces. The exposed germanium-based semiconductor undergoes annealing to form high carrier mobility nanowire structures. The nanowire structures can also be formed of different diameters by selective oxidation of some of the deposited germanium-based plugs. Alternately, forming fin structures of different widths results in deposited germanium plugs of different widths to be deposited to form different thicknesses of nanowires.

Abstract translation: 形成锗纳米线的方法包括形成包括交替的鳍和浅沟槽结构的半导体鳍结构，蚀刻翅片的顶部以形成翅片凹槽，并将锗基半导体作为基于锗的塞子沉积到翅片凹槽中。 该方法包括蚀刻浅沟槽结构以暴露锗基半导体侧面。 暴露的锗基半导体经历退火以形成高载流子迁移率纳米线结构。 纳米线结构也可以通过选择性氧化一些沉积的基于锗的塞子而由不同的直径形成。 或者，形成不同宽度的翅片结构导致沉积不同宽度的沉积的锗塞以形成不同厚度的纳米线。

公开(公告)号：US20160141386A1

公开(公告)日：2016-05-19

申请号：US14542685

申请日：2014-11-17

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： YU-HSIANG HUNG ,  YEN-LIANG WU ,  SSU-I FU ,  CHIH-KAI HSU ,  JYH-SHYANG JENQ

IPC: H01L29/66 ,  H01L21/266 ,  H01L21/033 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/66492 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/266 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/66795

Abstract: A method for forming a semiconductor device, includes steps of: providing a substrate; forming a first seal layer over the substrate; forming a second seal layer atop the first seal layer; forming a patterned photoresist layer on the second seal layer; implanting a dopant into the substrate by using the patterned photoresist layer as a mask; executing a first removing process to remove the patterned photoresist layer, wherein the first seal layer has a higher etch rate than that of the second seal layer in the first removing process; and removing the second seal layer after removing the patterned photoresist layer.

Abstract translation: 一种形成半导体器件的方法，包括以下步骤：提供衬底; 在所述基底上形成第一密封层; 在所述第一密封层的顶部形成第二密封层; 在所述第二密封层上形成图案化的光致抗蚀剂层; 通过使用图案化的光致抗蚀剂层作为掩模将掺杂剂注入到衬底中; 执行第一去除过程以去除图案化的光致抗蚀剂层，其中在第一去除过程中，第一密封层具有比第二密封层的蚀刻速率更高的蚀刻速率; 以及在去除图案化的光致抗蚀剂层之后去除第二密封层。

公开(公告)号：US20160086843A1

公开(公告)日：2016-03-24

申请号：US14957585

申请日：2015-12-02

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Ming-Shing Chen ,  Yu-Ting Wang ,  Ming-Hui Chang

IPC: H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/76224

Abstract: Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited to cover the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removed by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate is selectively removed.

Abstract translation: 半导体器件中的浅沟槽隔离结构及其制造方法。 该方法包括以下步骤。 衬底上设置衬垫氧化物层和其上的第一图案化的光刻胶层。 在对应于第一图案化光致抗蚀剂层的基板中形成第一沟槽。 第一介电层沉积在第一沟槽和衬底上。 提供第二图案化光致抗蚀剂层以在第一电介质层中形成开口，并且在衬底中形成对应于第二图案化光致抗蚀剂层的第二沟槽。 沉积第二电介质层以覆盖衬底中的第一沟槽和第二沟槽以及衬底上的第一介电层。 通过化学机械抛光除去第二介电层，直到暴露第一​​介电层。 选择性地去除衬底上的第一介电层。

公开(公告)号：US20160049506A1

公开(公告)日：2016-02-18

申请号：US14924734

申请日：2015-10-28

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Hsin-Ming HOU ,  Yu-Cheng TUNG ,  Ji-Fu KUNG ,  Wai-Yi LIEN ,  Ming-Tsung CHEN

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/76224 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a plurality of epitaxial structures is provided. The substrate has an active area defined by the isolation structures disposed within the substrate. That is, the active area is defined between the isolation structures. The gate structure is disposed on the substrate and located within the active area. The dummy gate structures are disposed on the substrate and located out of the active area. The edge of each dummy gate structure is separated from the boundary of the active area with a distance smaller than 135 angstroms. The epitaxial structures are disposed within the active area and in a portion of the substrate on two sides of the gate structure. The invention also provided a method for fabricating semiconductor device.

公开(公告)号：US09262820B2

公开(公告)日：2016-02-16

申请号：US14281881

申请日：2014-05-19

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Te-Hsien Hsieh ,  Ming-Jui Chen ,  Cheng-Te Wang ,  Jing-Yi Lee

IPC: G06K9/00 ,  G06T7/00 ,  G06K9/52

CPC classification number: G06T7/0004 ,  G03F1/36 ,  G03F7/70441 ,  G06K9/52

Abstract: A method for IC design is provided. Firstly, an IC design layout having a main feature with an original margin is received. Then, a first modified margin of the main feature is generated; and a first photolithography simulation procedure of the main feature with the first modified margin is performed to generate a first contour having a plurality of curves. Next, an equation of each of the curves is obtained; each equation of the curves is manipulated to obtain a vertex of each of the curves. After that, a first group of target points are assigned to the original margin. Each of the first group of target points respectively corresponds to one of the vertices. Finally, an optical proximity correction (OPC) procedure is performed by using the first group of target points to generate a second modified margin. An apparatus for IC design is also provided.

Abstract translation: 提供了一种IC设计方法。 首先，接收具有原始余量的主要特征的IC设计布局。 然后，生成主要特征的第一修改边缘; 并且执行具有第一修改余量的主要特征的第一光刻模拟程序以产生具有多个曲线的第一轮廓。 接着，求出各曲线的方程式， 操纵曲线的每个方程以获得每个曲线的顶点。 之后，将第一组目标点分配给原始边距。 第一组目标点中的每一个分别对应于一个顶点。 最后，通过使用第一组目标点来执行光学邻近校正（OPC）过程以产生第二修改余量。 还提供了用于IC设计的装置。

公开(公告)号：US20160018741A1

公开(公告)日：2016-01-21

申请号：US14470955

申请日：2014-08-28

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： EN-CHIUAN LIOU ,  TENG-CHIN KUO ,  YUAN-CHI PAI ,  CHUN-CHI YU

IPC: G03F7/20

CPC classification number: G03F7/70633

Abstract: An asymmetry compensation method used in a lithography overlay process and including steps of: providing a first substrate, wherein a circuit layout is disposed on the first substrate, a first mask layer and a second mask layer together having an x-axis allowable deviation range and an y-axis allowable deviation range relative to the circuit layout are stacked sequentially on the circuit layout, wherein the x-axis allowable deviation range is unequal to the y-axis allowable deviation range; and calculating an x-axis final compensation parameter and an y-axis final compensation parameter base on the unequal x-axis allowable deviation range and the y-axis allowable deviation range.

Abstract translation: 一种在光刻重叠工艺中使用的不对称补偿方法，包括以下步骤：提供第一衬底，其中电路布局设置在第一衬底上，第一掩模层和第二掩模层一起具有x轴允许偏差范围，以及 相对于电路布局的y轴允许偏差范围依次堆叠在电路布局上，其中x轴允许偏差范围不等于y轴允许偏差范围; 并且基于不等的x轴允许偏差范围和y轴允许偏差范围来计算x轴最终补偿参数和y轴最终补偿参数。

公开(公告)号：US20150355672A1

公开(公告)日：2015-12-10

申请号：US14819444

申请日：2015-08-06

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chien-Hung CHEN

IPC: G06F1/10

CPC classification number: G06F1/10 ,  G06F17/50 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/62 ,  G06F2217/84 ,  H01L23/522 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/17736 ,  H03K19/1774 ,  H01L2924/00

Abstract: An clock skew adjusting structure is provided. The clock skew adjusting structure includes a substrate, a wiring structure, a first active component and a second active component. The wiring structure includes at least a wiring layer and at least a via, the via is configured for different wiring layers to be electrically connected with each other. The first active component is formed on the substrate and configured for delivering a clock signal to the wiring structure. The second active component is formed on the substrate and electrically connected to the first active component through the wiring structure thus forming a timing path. The second active component receives the clock signal through the timing path.

Abstract translation: 提供了时钟偏移调整结构。 时钟偏移调整结构包括基板，布线结构，第一有源部件和第二有源部件。 所述布线结构至少包括布线层和至少一个通路，所述通孔被配置为不同的布线层以彼此电连接。 第一有源部件形成在衬底上并被配置为将时钟信号传送到布线结构。 第二有源部件形成在基板上，并且通过布线结构电连接到第一有源部件，从而形成定时路径。 第二有源分量通过定时路径接收时钟信号。

公开(公告)号：US09150407B2

公开(公告)日：2015-10-06

申请号：US13945892

申请日：2013-07-18

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Tzung-Han Tan ,  Bang-Chiang Lan ,  Ming-I Wang ,  Chien-Hsin Huang ,  Meng-Jia Lin

IPC: H04R31/00 ,  B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00246 ,  B81B3/0072 ,  B81B2203/04 ,  B81B2207/015 ,  B81C2201/0167

Abstract: A method for fabricating a microelectromechanical system (MEMS) device of the present invention includes the following steps: providing a substrate, comprising a circuit region and a MEMS region separated from each other; forming an interconnection structure on the substrate in the circuit region, and simultaneously forming a plurality of dielectric layers and a first electrode on the substrate in the MEMS region, wherein the first electrode comprises at least two metal layers formed in the dielectric layers and a protection ring formed in the dielectric layers and connecting two adjacent metal layers, so as to define an enclosed space between the two adjacent metal layers; forming a second electrode on the first electrode; and removing the dielectric layers outside the enclosed space in the MEMS region to form a cavity between the electrodes.

Abstract translation: 本发明的微机电系统（MEMS）器件的制造方法包括以下步骤：提供包括彼此分离的电路区域和MEMS区域的衬底; 在所述电路区域中的所述衬底上形成互连结构，并且在所述MEMS区域中的所述衬底上同时形成多个电介质层和第一电极，其中所述第一电极包括形成在所述电介质层中的至少两个金属层和保护层 环形成在电介质层中并连接两个相邻的金属层，以便限定两个相邻金属层之间的封闭空间; 在所述第一电极上形成第二电极; 并且去除MEMS区域中的封闭空间外的电介质层，以在电极之间形成空腔。