公开(公告)号：US20060145318A1

公开(公告)日：2006-07-06

申请号：US11150489

申请日：2005-06-10

申请人： Xiaotian Zhang ,  Kai Liu ,  Mlng Sun

发明人： Xiaotian Zhang ,  Kai Liu ,  Mlng Sun

IPC分类号： H01L23/495

CPC分类号： H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A DFN semiconductor package is disclosed. The package includes a leadframe having a die bonding pad formed integrally with a drain lead, a source lead bonding area and a gate lead bonding area, the source lead bonding area and the gate lead bonding area being of increased area, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead bonding area and a die gate bonding area coupled to the gate lead bonding area, and an encapsulant at least partially covering the die, drain lead, gate lead bonding area and source lead bonding area.

公开(公告)号：US09478646B2

公开(公告)日：2016-10-25

申请号：US13192385

申请日：2011-07-27

申请人： Anup Bhalla ,  Madhur Bobde ,  Yongping Ding ,  Xiaotian Zhang ,  Yueh-Se Ho

发明人： Anup Bhalla ,  Madhur Bobde ,  Yongping Ding ,  Xiaotian Zhang ,  Yueh-Se Ho

IPC分类号： H01L29/739 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/7395 ,  H01L21/2636 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/66333

摘要： A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.

摘要翻译： 用于制造阳极短路场效应绝缘栅双极晶体管（IGBT）的方法包括选择性地形成具有相反导电类型的第一和第二半导体注入区。 可以将第二导电类型的场阻挡层生长到衬底或植入衬底中。 外延层可以在衬底上或场停止层上生长。 在外延层内形成一个或多个绝缘栅双极晶体管（IGBT）元件单元。

公开(公告)号：US20150076676A1

公开(公告)日：2015-03-19

申请号：US14029555

申请日：2013-09-17

申请人： Jun Lu ,  François Hébert ,  Kai Liu ,  Xiaotian Zhang

发明人： Jun Lu ,  François Hébert ,  Kai Liu ,  Xiaotian Zhang

IPC分类号： H01L23/495 ,  H01L25/07

CPC分类号： H01L23/492 ,  H01L24/97 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/97 ,  H01L2924/13091 ,  H01L2924/15156 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00

摘要： A power semiconductor device package includes a conductive assembly including a connecting structure and a semiconductor die having an aperture formed therethrough, the aperture being sized and configured to spacedly receive the connecting structure. In an alternative embodiment, a power semiconductor device package includes a conductive assembly including a connecting structure and a pair of semiconductor die disposed on either side of the connecting structure in spaced relationship thereto.

摘要翻译： 功率半导体器件封装包括导电组件，其包括连接结构和具有穿过其形成的孔的半导体管芯，所述孔的尺寸和构造为间隔地接收连接结构。 在替代实施例中，功率半导体器件封装包括导电组件，该导电组件包括连接结构和设置在与之间隔开的连接结构的任一侧上的一对半导体管芯。

公开(公告)号：US08952509B1

公开(公告)日：2015-02-10

申请号：US14031283

申请日：2013-09-19

申请人： Hamza Yilmaz ,  Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Xiaotian Zhang ,  Zhi Qiang Niu ,  Ming-Chen Lu ,  Liang Zhao ,  YuPing Gong ,  GuoFeng Lian

发明人： Hamza Yilmaz ,  Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Xiaotian Zhang ,  Zhi Qiang Niu ,  Ming-Chen Lu ,  Liang Zhao ,  YuPing Gong ,  GuoFeng Lian

IPC分类号： H01L25/07 ,  H01L23/495 ,  H01L25/00

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： The present invention discloses a stacked dual MOSFET package structure and a preparation method thereof. The stacked dual MOSFET package structure comprises a lead frame unit having a die paddle, a first lead and a second lead; a first chip flipped and attached on a top surface of a main paddle of the die paddle; a second chip attached on a bottom surface of the main paddle; and a metal clip mounted on the back of the flipped first chip and electrically connecting an electrode at the back of the first chip to the first lead. A top surface of a metal bump arranged on each electrode at the front of the second chip, a bottom surface of the die pin of the die paddle, a bottom surface of a lead pin of the second lead, and a bottom surface of the first lead are located on the same plane.

摘要翻译： 本发明公开了一种叠层双MOSFET封装结构及其制备方法。 堆叠双MOSFET封装结构包括具有管芯焊盘，第一引线和第二引线的引线框架单元; 第一芯片翻转并附接在模板的主桨的顶表面上; 附接在主桨的底表面上的第二芯片; 以及安装在翻转的第一芯片的背面上并将第一芯片背面的电极电连接到第一引线的金属夹。 布置在第二芯片的前面的每个电极上的金属凸块的顶表面，模板的模具销的底表面，第二引线的引脚的底表面和第一引脚的底表面 导线位于同一平面上。

公开(公告)号：US08344519B2

公开(公告)日：2013-01-01

申请号：US13089065

申请日：2011-04-18

申请人： Jun Lu ,  Allen Chang ,  Xiaotian Zhang

发明人： Jun Lu ,  Allen Chang ,  Xiaotian Zhang

IPC分类号： H01L23/48

CPC分类号： H01L21/823487 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/58 ,  H01L24/37 ,  H01L24/39 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/91 ,  H01L25/071 ,  H01L25/074 ,  H01L25/18 ,  H01L27/088 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H02J7/0031 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A battery protection package assembly is disclosed. The assembly includes a power control integrated circuit (IC) with pins for a supply voltage input (VCC) and a ground (VSS) on a first side of the power control IC. First and second common-drain metal oxide semiconductor field effect transistors (MOSFETs) are electrically coupled to the power control IC. The power control IC and the first and second common-drain metal oxide semiconductor field effect transistors (MOSFET) are co-packaged on a common die pad. The power control IC is vertically stacked on top of one or more of the first and second common-drain MOSFETs. Leads coupled to a supply voltage input (VCC) and a ground (VSS) of the power control IC are on a first side of the common die pad.

摘要翻译： 公开了一种电池保护封装组件。 该组件包括功率控制集成电路（IC），其具有用于功率控制IC的第一侧上的电源电压输入（VCC）和接地（VSS）的引脚。 第一和第二共漏极金属氧化物半导体场效应晶体管（MOSFET）电耦合到功率控制IC。 功率控制IC和第一和第二共漏极金属氧化物半导体场效应晶体管（MOSFET）共同封装在公共管芯焊盘上。 功率控制IC垂直堆叠在第一和第二共漏极MOSFET中的一个或多个的顶部上。 耦合到功率控制IC的电源电压输入（VCC）和接地（VSS）的引线位于公共管芯焊盘的第一侧上。

公开(公告)号：US08222088B2

公开(公告)日：2012-07-17

申请号：US12799811

申请日：2010-04-30

申请人： Xiaotian Zhang ,  Jun Lu

发明人： Xiaotian Zhang ,  Jun Lu

IPC分类号： H01L21/60 ,  H01L21/78

CPC分类号： H01L24/37 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/27 ,  H01L24/29 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/84 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/0603 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/49111 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/8585 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive material is applied onto the chip carrier and the pin of the lead frame and also on the front electrode of the semiconductor chip via pre-printing. The back of the semiconductor chip is adhered on the chip carrier, and the front electrode of the semiconductor chip and the pin are connected respectively with a metal connector. The size, shape and thickness of the adhesive material are applied according to different application requirements according to size and shapes of the contact zone of the semiconductor chip and the metal connector. Particularly, the adhesive zones are formed by pre-printing the adhesive material thus significantly enhance the quality and performance of semiconductor products, and improves the productivity.

摘要翻译： 本发明公开了一种半导体封装，其具有预先印刷在引线框架和芯片上的粘合剂材料及其制造方法。 粘合剂材料通过预打印被施加到芯片载体和引线框架的引脚以及半导体芯片的前电极上。 半导体芯片的背面粘附在芯片载体上，并且半导体芯片的前电极和引脚分别与金属连接器连接。 根据不同的应用要求，根据半导体芯片和金属连接器的接触区域的尺寸和形状来施加粘合材料的尺寸，形状和厚度。 特别地，通过预先印刷粘合剂材料形成粘合剂区域，从而显着提高半导体产品的质量和性能，并提高生产率。

公开(公告)号：US20120166660A1

公开(公告)日：2012-06-28

申请号：US13409897

申请日：2012-03-01

申请人： Xiaotian ZHANG ,  Junxia XU ,  Huangwei WU

发明人： Xiaotian ZHANG ,  Junxia XU ,  Huangwei WU

IPC分类号： G06F15/16

CPC分类号： H04L12/2809 ,  H04L12/2836 ,  H04L41/0213

摘要： A method, a system for accessing a home network device, and a home network access device are disclosed. The method includes the steps as follows. A home network access device finds a home network device and obtains information of the home network device through a home network protocol. A data model of the home network device is established in the home network access device according to the information of the home network device. A remote service device accesses the data model of the home network device established in the home network access device through a remote management protocol.

摘要翻译： 公开了一种方法，用于接入家庭网络设备的系统和家庭网络接入设备。 该方法包括以下步骤。 家庭网络接入设备通过家庭网络协议找到家庭网络设备并获得家庭网络设备的信息。 家庭网络设备的数据模型根据家庭网络设备的信息在家庭网络接入设备中建立。 远程服务设备通过远程管理协议访问家庭网络接入设备中建立的家庭网络设备的数据模型。

公开(公告)号：US08049315B2

公开(公告)日：2011-11-01

申请号：US13007279

申请日：2011-01-14

申请人： Jun Lu ,  Anup Bhalla ,  Xiaobin Wang ,  Allen Chang ,  Kenny Man Sheng Hu ,  Xiaotian Zhang

发明人： Jun Lu ,  Anup Bhalla ,  Xiaobin Wang ,  Allen Chang ,  Kenny Man Sheng Hu ,  Xiaotian Zhang

IPC分类号： H01L23/495

CPC分类号： H01L21/823487 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/58 ,  H01L24/37 ,  H01L24/39 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/91 ,  H01L25/071 ,  H01L25/074 ,  H01L25/18 ,  H01L27/088 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H02J7/0031 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A semiconductor package assembly may include a lead frame having a die bonding pad and plurality of leads coupled to the first die bonding pad. A vertical semiconductor device may be bonded to the die bonding pad. The device may have a conductive pad electrically connected to one lead through a first bond wire. An electrically isolated conductive trace may be formed from a layer of conductive material of the first semiconductor device. The conductive trace provides an electrically conductive path between the first bond wire and a second bond wire. The conductive path may either pass underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or the conductive path may result in a reduced length for the first and second bond wires that is less than a predetermined maximum length.

摘要翻译： 半导体封装组件可以包括引线框架，其具有管芯接合焊盘和耦合到第一管芯接合焊盘的多个引线。 垂直半导体器件可以结合到芯片焊盘。 该器件可以具有通过第一接合线电连接到一个引线的导电焊盘。 电绝缘的导电迹线可以由第一半导体器件的导电材料层形成。 导电迹线在第一接合线和第二接合线之间提供导电路径。 导电路径可以通过第三接合线下方，从而避免第三接合线穿过另一接合线，或者导电路径可导致第一和第二接合线的长度小于预定最大长度。

公开(公告)号：US20110108998A1

公开(公告)日：2011-05-12

申请号：US13007279

申请日：2011-01-14

申请人： Jun Lu ,  Anup Bhalla ,  Xiaobin Wang ,  Allen Chang ,  Man Sheng Hu ,  Xiaotian Zhang

发明人： Jun Lu ,  Anup Bhalla ,  Xiaobin Wang ,  Allen Chang ,  Man Sheng Hu ,  Xiaotian Zhang

IPC分类号： H01L23/52

CPC分类号： H01L21/823487 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/58 ,  H01L24/37 ,  H01L24/39 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/91 ,  H01L25/071 ,  H01L25/074 ,  H01L25/18 ,  H01L27/088 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H02J7/0031 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A semiconductor package assembly may include a lead frame having a die bonding pad and plurality of leads coupled to the first die bonding pad. A vertical semiconductor device may be bonded to the die bonding pad. The device may have a conductive pad electrically connected to one lead through a first bond wire. An electrically isolated conductive trace may be formed from a layer of conductive material of the first semiconductor device. The conductive trace provides an electrically conductive path between the first bond wire and a second bond wire. The conductive path may either pass underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or the conductive path may result in a reduced length for the first and second bond wires that is less than a predetermined maximum length.

摘要翻译： 半导体封装组件可以包括引线框架，其具有管芯接合焊盘和耦合到第一管芯接合焊盘的多个引线。 垂直半导体器件可以结合到芯片焊盘。 该器件可以具有通过第一接合线电连接到一个引线的导电焊盘。 电绝缘的导电迹线可以由第一半导体器件的导电材料层形成。 导电迹线在第一接合线和第二接合线之间提供导电路径。 导电路径可以通过第三接合线下方，从而避免第三接合线穿过另一接合线，或者导电路径可导致第一和第二接合线的长度小于预定最大长度。

公开(公告)号：US07884696B2

公开(公告)日：2011-02-08

申请号：US12011489

申请日：2008-01-25

申请人： François Hébert ,  Tao Feng ,  Xiaotian Zhang ,  Jun Lu

发明人： François Hébert ,  Tao Feng ,  Xiaotian Zhang ,  Jun Lu

IPC分类号： H01F5/00

CPC分类号： H01F17/062

摘要： A lead frame-based discrete power inductor is disclosed. The power inductor includes top and bottom lead frames, the leads of which form a coil around a single closed-loop magnetic core. The coil includes interconnections between inner and outer contact sections of the top and bottom lead frames, the magnetic core being sandwiched between the top and bottom lead frames. Ones of the leads of the top and bottom lead frames have a generally non-linear, stepped configuration such that the leads of the top lead frame couple adjacent leads of the bottom lead frame about the magnetic core to form the coil.