公开(公告)号：US06699780B1

公开(公告)日：2004-03-02

申请号：US10302642

申请日：2002-11-23

申请人： Cheng-Lien Chiang ,  Charles W. C. Lin

发明人： Cheng-Lien Chiang ,  Charles W. C. Lin

IPC分类号： H01L2144

CPC分类号： H01L24/11 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/1134 ,  H01L2224/1148 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/3025 ,  H05K3/4046 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05124

摘要： A method of connecting a conductive trace to a semiconductor chip includes providing a semiconductor chip with upper and lower surfaces, wherein the upper surface includes a conductive pad, providing a conductive trace, then disposing an insulative adhesive between the conductive trace and the chip, thereby mechanically attaching the conductive trace to the chip such that the conductive trace overlaps the pad, the adhesive contacts and is sandwiched between the conductive trace and the pad, and the conductive trace and the pad are electrically isolated from one another, then removing the adhesive between the conductive trace and the pad, and then forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, the adhesive is removed by laser ablation then plasma etching.

摘要翻译： 将导电迹线连接到半导体芯片的方法包括向半导体芯片提供上表面和下表面，其中上表面包括导电焊盘，提供导电迹线，然后在导电迹线和芯片之间设置绝缘粘合剂，从而 将导电迹线机械地附接到芯片，使得导电迹线与焊盘重叠，粘合剂接触并夹在导电迹线和焊盘之间，并且导电迹线和焊盘彼此电隔离，然后将粘合剂 导电迹线和焊盘，然后形成接触和电连接导电迹线和焊盘的连接接头。 优选地，通过激光烧蚀等离子体蚀刻去除粘合剂。

公开(公告)号：US06608374B1

公开(公告)日：2003-08-19

申请号：US10215944

申请日：2002-08-09

申请人： Charles W. C. Lin ,  Cheng-Lien Chiang

发明人： Charles W. C. Lin ,  Cheng-Lien Chiang

IPC分类号： H01L2348

CPC分类号： H01L24/11 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/1134 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/4046 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05644

摘要： A method of connecting a conductive trace to a semiconductor chip includes providing a semiconductor chip, a conductive trace and a base, wherein the chip includes a conductive pad, the base includes a recess, the conductive trace includes a bumped terminal in the recess, the bumped terminal includes a cavity that extends into and faces away from the recess, the base contacts and covers the conductive trace on a side opposite the chip, and the conductive trace and the base are different metals, mechanically attaching the chip to the conductive trace using an insulative adhesive that extends into the cavity, etching the base to expose the conductive trace, and forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, the bumped terminal is inside a periphery of the chip, and the adhesive fills the cavity.

摘要翻译： 将导电迹线连接到半导体芯片的方法包括提供半导体芯片，导电迹线和基底，其中所述芯片包括导电焊盘，所述基底包括凹部，所述导电迹线包括在所述凹部中的凸起端子， 凸起端子包括延伸到凹部内并远离凹部的空腔，基部在与芯片相对的一侧上接触并覆盖导电迹线，并且导电迹线和基座是不同的金属，使用 延伸到空腔中的绝缘粘合剂，蚀刻基底以暴露导电迹线，以及形成接触和电连接导电迹线和焊盘的连接接头。 优选地，凸起端子在芯片的周边内，并且粘合剂填充空腔。

公开(公告)号：US06576493B1

公开(公告)日：2003-06-10

申请号：US10188459

申请日：2002-07-03

申请人： Charles W. C. Lin ,  Cheng-Lien Chiang

发明人： Charles W. C. Lin ,  Cheng-Lien Chiang

IPC分类号： H01L2144

CPC分类号： H01L23/5389 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/1134 ,  H01L2224/11474 ,  H01L2224/13008 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K3/4046 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/48

摘要： A method of making a semiconductor chip assembly includes providing a semiconductor chip, a metal base, an insulative base and a conductive trace, wherein the chip includes a conductive pad, the metal base is disposed on a side of the insulative base that faces away from the chip, and the conductive trace includes a contact terminal that extends through the insulative base, then forming an opening that extends through the metal base and the insulative base, exposes the pad and is spaced from the contact terminal, then forming a connection joint that contacts and electrically connects the conductive trace and the pad, and then removing a portion of the metal base that contacts the contact terminal. Preferably, the opening extends through an insulative adhesive that attaches the chip to the conductive trace.

摘要翻译： 制造半导体芯片组件的方法包括提供半导体芯片，金属基底，绝缘基底和导电迹线，其中芯片包括导电垫，金属基底设置在绝缘基底的远离 芯片和导电迹线包括延伸穿过绝缘基底的接触端子，然后形成延伸穿过金属基底和绝缘基底的开口，露出垫并与接触端子间隔开，然后形成连接接头， 接触并电连接导电迹线和焊盘，然后去除与接触端子接触的金属基体的一部分。 优选地，开口延伸穿过将芯片附接到导电迹线的绝缘粘合剂。

公开(公告)号：US06492252B1

公开(公告)日：2002-12-10

申请号：US09997973

申请日：2001-11-29

申请人： Charles W. C. Lin ,  Cheng-Lien Chiang

发明人： Charles W. C. Lin ,  Cheng-Lien Chiang

IPC分类号： H01L2144

CPC分类号： H01L24/11 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/1134 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/4046 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05644

摘要： A method of connecting a conductive trace to a semiconductor chip includes providing a semiconductor chip, a conductive trace and a base, wherein the chip includes a conductive pad, the base includes a recess, the conductive trace includes a bumped terminal in the recess, the bumped terminal includes a cavity that extends into and faces away from the recess, the base contacts and covers the conductive trace on a side opposite the chip, and the conductive trace and the base are different metals, mechanically attaching the chip to the conductive trace using an insulative adhesive that extends into the cavity, etching the base to expose the conductive trace, and forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, the bumped terminal is inside a periphery of the chip, and the adhesive fills the cavity.

摘要翻译： 将导电迹线连接到半导体芯片的方法包括提供半导体芯片，导电迹线和基底，其中所述芯片包括导电焊盘，所述基底包括凹部，所述导电迹线包括在所述凹部中的凸起端子， 凸起端子包括延伸到凹部内并远离凹部的空腔，基部在与芯片相对的一侧上接触并覆盖导电迹线，并且导电迹线和基座是不同的金属，使用 延伸到空腔中的绝缘粘合剂，蚀刻基底以暴露导电迹线，以及形成接触和电连接导电迹线和焊盘的连接接头。 优选地，凸起端子在芯片的周边内，并且粘合剂填充空腔。

公开(公告)号：US07871274B2

公开(公告)日：2011-01-18

申请号：US12509757

申请日：2009-07-27

申请人： Cheng-Lien Chiang

发明人： Cheng-Lien Chiang

IPC分类号： H01R12/00 ,  H05K1/00

CPC分类号： H05K3/325 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/42 ,  H05K7/1069 ,  H05K2201/049 ,  H05K2201/10265 ,  H05K2201/10378 ,  H05K2201/10734

摘要： An integrated circuit (IC) adapter is disclosed to be adaptive sandwiched in between a ball grid array (BGA) integrated circuit (IC) and a printed circuit board to electrically couple the ball grid array IC and the printed circuit board. The IC adapter has a plurality of through holes therein, a resilient element in each of the through hole; in combination with a binding element for binding the integrated circuit (IC) onto the IC adapter such that the ball grid array IC can be removed, manually and without using any maintenance tool, from the IC adapter.

摘要翻译： 公开了一种集成电路（IC）适配器，以适应性地夹在球栅阵列（BGA）集成电路（IC）和印刷电路板之间，以电耦合球栅阵列IC和印刷电路板。 IC适配器在其中具有多个通孔，每个通孔中具有弹性元件; 与用于将集成电路（IC）绑定到IC适配器上的绑定元件组合，使得可以手动地并且不使用任何维护工具从IC适配器移除球栅阵列IC。

公开(公告)号：US07622795B2

公开(公告)日：2009-11-24

申请号：US11749150

申请日：2007-05-15

申请人： Cheng-Lien Chiang

发明人： Cheng-Lien Chiang

IPC分类号： H01L23/495

CPC分类号： F21K9/00 ,  F21K9/232 ,  F21Y2107/30 ,  F21Y2107/40 ,  F21Y2115/10 ,  H01L2224/49113

摘要： A substrate structure for light emitting diodes (LED) chips operation includes a heat spreader, chip holders arranged in the center of the heat spreader, transfer pads located near the chip holders for wire bonding interconnection between the LED chips, and a circuit layer having a gap dividing the circuit layer diagonally. The circuit layer includes a first insulation layer on top of the heat spreader, a metal trace layer on top of the first insulation layer, and a second insulation layer on top of the metal trace layer, wherein portions of the second insulation layer are removed at the opposite corners along the gap, and around the opening, and a conductive plating is plated on the second insulation layer around the opening. Furthermore, a spotlight cap is provided to focus the light emitted from the LED. A LED package includes the substrate structure and the spotlight cap is also provided.

摘要翻译： 用于发光二极管（LED）芯片操作的衬底结构包括散热器，布置在散热器中心的芯片保持器，位于芯片保持器附近的转移垫，用于LED芯片之间的引线键合互连，以及具有 对角线间隔电路层的间隙。 电路层包括在散热器顶部的第一绝缘层，在第一绝缘层的顶部上的金属迹线层，以及在金属迹线层的顶部上的第二绝缘层，其中第二绝缘层的部分在 沿着间隙的相对的角落，并且围绕开口，并且在开口周围的第二绝缘层上镀覆导电电镀。 此外，提供聚光灯帽以聚焦从LED发射的光。 LED封装包括基板结构，还提供聚光灯盖。

公开(公告)号：US20090206481A1

公开(公告)日：2009-08-20

申请号：US12430216

申请日：2009-04-27

申请人： Cheng-Lien Chiang

发明人： Cheng-Lien Chiang

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H05K3/368 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49811 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/4824 ,  H01L2224/4826 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H05K3/244 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/10234 ,  H05K2201/10666 ,  H05K2203/041 ,  H05K2203/0455 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An interconnection mechanism between plated through holes is disclosed, a first embodiment includes a first substrate having a first plated through hole; a second substrate having a second plated through hole; a metal core is configured in between the two plated through holes; the metal ball has a diameter larger than a diameter of the plated through holes; and melted solder binds the first plated through hole, metal core, and the second plated through hole. A second embodiment includes stacked substrate having a gold plated only on ring pads of the plated through holes; melted solder binds the two gold ring pads.

摘要翻译： 公开了电镀通孔之间的互连机构，第一实施例包括具有第一电镀通孔的第一基板; 具有第二电镀通孔的第二基板; 金属芯构造在两个电镀通孔之间; 金属球的直径大于电镀通孔的直径; 并且熔化的焊料结合第一电镀通孔，金属芯和第二电镀通孔。 第二实施例包括具有仅在电镀通孔的环形垫上镀金的堆叠衬底; 熔化的焊料结合两个金环垫。

公开(公告)号：US06774659B1

公开(公告)日：2004-08-10

申请号：US10059475

申请日：2002-01-29

申请人： Cheng-Lien Chiang

发明人： Cheng-Lien Chiang

IPC分类号： G01R3102

CPC分类号： H01L24/06 ,  H01L21/4821 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/4952 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/45144 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S439/912 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method of testing a semiconductor package device includes providing a device that includes an insulative housing, a semiconductor chip, a terminal and a lead, wherein the terminal protrudes downwardly from and extends through a bottom surface of the housing, the lead protrudes laterally from and extends through a side surface of the housing, and the terminal and the lead are electrically connected to one another and a chip pad inside the housing, attaching the device to a test socket that electrically contacts the lead without electrically contacting the terminal, testing the test socket, and removing the device from the test socket. The method may include trimming the lead after removing the device from the test socket and the attaching the device to a printed circuit board that electrically contacts the terminal without electrically contacting the lead.

摘要翻译： 一种测试半导体封装器件的方法包括提供一种包括绝缘壳体，半导体芯片，端子和引线的器件，其中端子从壳体的底表面向下突出并延伸穿过壳体的底表面， 延伸穿过壳体的侧表面，并且端子和引线彼此电连接并且壳体内部具有芯片焊盘，将该装置附接到测试插座，该测试插座与导线电接触而不与端子电接触，测试测试 插座，并从设备上拔下测试插座。 该方法可以包括在从测试插座中取出装置之后修整导线，以及将装置附接到与端子电接触而不与导线接触的印刷电路板。

公开(公告)号：US06259266B1

公开(公告)日：2001-07-10

申请号：US09179408

申请日：1998-10-27

申请人： Cheng-Lien Chiang ,  Shyi-Ching Liau

发明人： Cheng-Lien Chiang ,  Shyi-Ching Liau

IPC分类号： G01R3128

CPC分类号： G01R1/0483 ,  G01R1/0408

摘要： A testing means for holding chips to perform tests comprises of a plurality of inner leads for providing electrical connection for the chips with a plurality of conductive bumps. A metal layer is formed on surfaces of the plurality of inner leads for fixing the chips on the plurality of inner leads, wherein a melting point of the metal layer is below a melting point of the conductive bumps. Then, a adhesive material is pasted on a bottom surface of the plurality of inner leads for fixing the plurality of inner leads. A holding means is used to connect and hold the plurality of inner leads, and used for providing electrical connection for the plurality of inner leads.

摘要翻译： 用于保持芯片进行测试的测试装置包括多个内引线，用于为芯片提供多个导电凸块的电连接。 在多个内引线的表面上形成金属层，用于将芯片固定在多个内引线上，其中金属层的熔点低于导电凸块的熔点。 然后，将粘合剂材料粘贴在多个内引线的底表面上，用于固定多根内引线。 保持装置用于连接和保持多个内引线，并用于为多个内引线提供电连接。

公开(公告)号：US5942907A

公开(公告)日：1999-08-24

申请号：US852470

申请日：1997-05-07

申请人： Cheng-Lien Chiang

发明人： Cheng-Lien Chiang

IPC分类号： G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  G01R31/02

CPC分类号： G01R31/2886

摘要： In accordance with the present invention, a test board for connecting a bare die to a leadframe for testing the die is provided. The test board has a conducting surface on a bottom portion of the board that is adapted to engage and electrically connect to a lead finger in the leadframe. A tape automated bonding tape which has a conductive lead and a first and a second conductive bump are provided where the first conductive bump is situated on an upper surface of the lead and the second conductive bump is situated on a bottom surface of the lead. The first and second conductive bumps establish an electrical communication between the bumps throughout the conductive lead. The first conductive bump is also connected to the conducting surface of the board and the second bump is adapted to engage in I/O pad so that the bare die may be tested through the leadframe.

摘要翻译： 根据本发明，提供了一种用于将裸模连接到用于测试模具的引线框的测试板。 测试板在板的底部具有导电表面，该导电表面适于与引线框架中的引线接合并电连接。 提供了具有导电引线和第一和第二导电凸块的带状自动粘结带，其中第一导电凸块位于引线的上表面上，第二导电凸块位于引线的底表面上。 第一和第二导电凸块在整个导电引线之间建立凸块之间的电连通。 第一导电凸起还连接到板的导电表面，并且第二凸起适于接合I / O焊盘，使得裸芯可以通过引线框架进行测试。