公开(公告)号：US08749059B2

公开(公告)日：2014-06-10

申请号：US13418261

申请日：2012-03-12

申请人： Mukta G. Farooq ,  Emily R. Kinser ,  Ian D. Melville ,  Krystyna Waleria Semkow

发明人： Mukta G. Farooq ,  Emily R. Kinser ,  Ian D. Melville ,  Krystyna Waleria Semkow

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/02697 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05007 ,  H01L2224/05016 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05187 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/15787 ,  H01L2924/04953 ,  H01L2924/01014 ,  H01L2224/05552 ,  H01L2924/00

摘要： Disclosed is a process of making a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. There may also be a cap layer over the copper plug to protect it from oxidation. There may also be a dielectric layer over the cap layer.

摘要翻译： 公开了制造半导体器件的方法，其中绝缘层具有与器件的最后布线层接触的铜插塞。 还可以存在将铜塞与绝缘层分离的阻挡层。 在铜塞上方也可能有一个盖层，以防止它被氧化。 在盖层上还可以存在介电层。

公开(公告)号：US08445374B2

公开(公告)日：2013-05-21

申请号：US13361057

申请日：2012-01-30

申请人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca

发明人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca

IPC分类号： H01L21/44

CPC分类号： H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

摘要： A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.

摘要翻译： 一种方法产生一种结构，其包括通过柱和开口连接到集成电路芯片的载体。 因此，在这种结构中，至少一个导电柱与集成电路芯片的表面延伸一段距离或高度，并且阻挡层围绕导电柱的下部，使得阻挡层覆盖柱的高度的至少一部分 最接近芯片表面。 载体中至少有一个开口足够大以容纳导电柱和屏障，并且导电柱和屏障位于开口中。 在开口的底部使用焊料将导电柱连接到开口的底部。 屏障防止焊料接触由屏障保护的导电柱的部分。

公开(公告)号：US20100019354A1

公开(公告)日：2010-01-28

申请号：US12573364

申请日：2009-10-05

申请人： Mukta G. Farooq ,  Dae-Young Jung ,  Ian D. Melville

发明人： Mukta G. Farooq ,  Dae-Young Jung ,  Ian D. Melville

IPC分类号： H01L23/58 ,  H01L23/544

CPC分类号： H01L21/67092 ,  H01L21/78 ,  H01L23/562 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention is directed to an improved semiconductor chip that reduces crack initiation and propagation into the active area of a semiconductor chip. A semiconductor wafer includes dicing channels that separate semiconductor chips and holes through a portion of a semiconductor chip, which are located at the intersection of the dicing channels. Once diced from the semiconductor wafer, semiconductor chips are created without ninety degree angle corners.

摘要翻译： 本发明涉及一种改进的半导体芯片，其减少裂纹发生和传播到半导体芯片的有源区域。 半导体晶片包括分开半导体芯片和穿过半导体芯片的位于切割通道的交叉点的部分的切割通道。 一旦从半导体晶片切割，半导体芯片就不会产生90度角角。

公开(公告)号：US07622737B2

公开(公告)日：2009-11-24

申请号：US11776114

申请日：2007-07-11

申请人： Mukta G. Farooq ,  Xiao H. Liu ,  Ian D. Melville

发明人： Mukta G. Farooq ,  Xiao H. Liu ,  Ian D. Melville

IPC分类号： H01L23/58 ,  H01L21/00

CPC分类号： G01R31/2853 ,  H01L22/34 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00012

摘要： Test structures for electrically detecting BEOL failures are provided. In an embodiment, the structure comprises: an input/output connection disposed above a primary conductive pad which is embedded in an insulator; a dielectric layer disposed upon the insulator; a primary via extending through the dielectric layer down to the primary conductive pad for providing electrical connection between the input/output connection and the primary conductive pad; and a secondary via filled with a conductive material in electrical connection with the input/output connection, the secondary via extending through the dielectric layer down to a secondary interconnect in electrical connection with a secondary conductive pad that is insulated from the primary conductive pad.

摘要翻译： 提供电气检测BEOL故障的测试结构。 在一个实施例中，该结构包括：输入/输出连接，其布置在嵌入绝缘体中的主导电垫上方; 设置在绝缘体上的电介质层; 主通孔延伸穿过介电层到主导电焊盘，用于在输入/输出连接和主导电焊盘之间提供电连接; 以及填充有与所述输入/输出连接电连接的导电材料的次级通孔，所述次级通孔延伸穿过所述电介质层到与所述主导电焊盘绝缘的次级导电焊盘电连接的次互连。

公开(公告)号：US20120161300A1

公开(公告)日：2012-06-28

申请号：US13409643

申请日：2012-03-01

申请人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

发明人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

IPC分类号： H01L23/552

CPC分类号： H01L23/5329 ,  H01L23/556 ,  H01L2924/0002 ,  Y10S438/958 ,  Y10S438/967 ,  H01L2924/00

摘要： Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.

摘要翻译： 公开了阻止电离辐射以减少软错误的方法和产生的IC芯片。 一个实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及在其中形成包括其中的电离辐射阻挡材料的至少一个后端线（BEOL）电介质层。 另一实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及形成位于IC芯片的后端（BEOL）的电离辐射阻挡层。 电离辐射阻挡材料或层吸收电离辐射并减少IC芯片内的软误差。

公开(公告)号：US20120135564A1

公开(公告)日：2012-05-31

申请号：US13361057

申请日：2012-01-30

申请人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca

发明人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca

IPC分类号： H01L21/60

CPC分类号： H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

摘要： A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.

摘要翻译： 一种方法产生一种结构，其包括通过柱和开口连接到集成电路芯片的载体。 因此，在这种结构中，至少一个导电柱与集成电路芯片的表面延伸一段距离或高度，并且阻挡层围绕导电柱的下部，使得阻挡层覆盖柱的高度的至少一部分 最接近芯片表面。 载体中至少有一个开口足够大以容纳导电柱和屏障，并且导电柱和屏障位于开口中。 在开口的底部使用焊料将导电柱连接到开口的底部。 屏障防止焊料接触由屏障保护的导电柱的部分。

公开(公告)号：US07867887B2

公开(公告)日：2011-01-11

申请号：US12174074

申请日：2008-07-16

申请人： Ian D. Melville ,  Mukta G. Farooq ,  Dae Young Jung

发明人： Ian D. Melville ,  Mukta G. Farooq ,  Dae Young Jung

IPC分类号： H01L21/768

CPC分类号： H01L24/05 ,  H01L24/13 ,  H01L2224/02235 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552

摘要： The present invention provides bond pads structures between semiconductor integrated circuits and the chip package with enhanced resistance to fracture and improved reliability. Mismatch in the coefficient of temperature expansion (CTE) among the materials used in bond structures induces stress and shear on them that may result in fractures within the back end dielectric stacks and cause reliability problems of the packaging. By placing multiple metal pads which are connected to the bond pad through multiple metal via, the adhesion between the bond pads and the back end dielectric stacks is enhanced.

摘要翻译： 本发明提供了半导体集成电路和芯片封装之间的接合焊盘结构，其具有增强的抗断裂性和改进的可靠性。 在粘结结构中使用的材料之间的温度膨胀系数（CTE）的不匹配会对其造成应力和剪切，这可能导致后端介质堆叠中的断裂，并导致包装的可靠性问题。 通过设置通过多个金属通孔连接到接合焊盘的多个金属焊盘，增强了接合焊盘和后端电介质叠层之间的粘附力。

公开(公告)号：US20090015285A1

公开(公告)日：2009-01-15

申请号：US11776114

申请日：2007-07-11

申请人： Mukta G. Farooq ,  Xiao H. Liu ,  Ian D. Melville

发明人： Mukta G. Farooq ,  Xiao H. Liu ,  Ian D. Melville

IPC分类号： G01R31/26 ,  H01L21/4763 ,  H01L23/58

CPC分类号： G01R31/2853 ,  H01L22/34 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00012

摘要： Test structures for electrically detecting BEOL failures are provided. In an embodiment, the structure comprises: an input/output connection disposed above a primary conductive pad which is embedded in an insulator; a dielectric layer disposed upon the insulator; a primary via extending through the dielectric layer down to the primary conductive pad for providing electrical connection between the input/output connection and the primary conductive pad; and a secondary via filled with a conductive material in electrical connection with the input/output connection, the secondary via extending through the dielectric layer down to a secondary interconnect in electrical connection with a secondary conductive pad that is insulated from the primary conductive pad.

摘要翻译： 提供电气检测BEOL故障的测试结构。 在一个实施例中，该结构包括：输入/输出连接，其布置在嵌入绝缘体中的主导电垫上方; 设置在绝缘体上的电介质层; 主通孔延伸穿过介电层到主导电焊盘，用于在输入/输出连接和主导电焊盘之间提供电连接; 以及填充有与所述输入/输出连接电连接的导电材料的次级通孔，所述次级通孔延伸穿过所述电介质层到与所述主导电焊盘绝缘的次级导电焊盘电连接的次互连。

公开(公告)号：US07470985B2

公开(公告)日：2008-12-30

申请号：US11461208

申请日：2006-07-31

申请人： Mukta G. Farooq ,  Laertis Economikos ,  Ian D. Melville ,  Kevin S. Petrarca ,  Richard P. Volant

发明人： Mukta G. Farooq ,  Laertis Economikos ,  Ian D. Melville ,  Kevin S. Petrarca ,  Richard P. Volant

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05085 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： Disclosed are embodiments of a far back end of the line solder connector and a method of forming the connector that eliminates the use aluminum, protects the integrity of the ball limiting metallurgy (BLM) layers and promotes adhesion of the BLM layers by incorporating a thin conformal conductive liner into the solder connector structure. This conductive liner coats the top of the via filling in any divots in order to create a uniform surface for BLM deposition and to, thereby, protect the integrity of the BLM layers. The liner further coats the dielectric sidewalls of the well in which the BLM layers are formed in order to enhance adhesion of the BLM layers to the well.

摘要翻译： 公开了线焊料连接器的远端的实施例以及形成连接器的方法，其消除了使用铝，保护了球限制冶金（BLM）层的完整性，并且通过并入薄的保形膜来促进BLM层的粘附 导电衬里进入焊接接头结构。 该导电衬里以通孔填充物的顶部涂覆任何刻痕，以便产生用于BLM沉积的均匀表面，从而保护BLM层的完整性。 衬垫还涂覆在其中形成BLM层的阱的电介质侧壁，以便增强BLM层与阱的粘合性。

公开(公告)号：US20080150087A1

公开(公告)日：2008-06-26

申请号：US11615236

申请日：2006-12-22

申请人： Mukta G. Farooq ,  Dae-Young Jung ,  Ian D. Melville

发明人： Mukta G. Farooq ,  Dae-Young Jung ,  Ian D. Melville

IPC分类号： H01L23/544 ,  H01L21/00

CPC分类号： H01L21/67092 ,  H01L21/78 ,  H01L23/562 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention is directed to an improved semiconductor chip that reduces crack initiation and propagation into the active area of a semiconductor chip. A semiconductor wafer includes dicing channels that separate semiconductor chips and holes through a portion of a semiconductor chip, which are located at the intersection of the dicing channels. Once diced from the semiconductor wafer, semiconductor chips are created without ninety degree angle corners.

摘要翻译： 本发明涉及一种改进的半导体芯片，其减少裂纹发生和传播到半导体芯片的有源区域。 半导体晶片包括分开半导体芯片和穿过半导体芯片的位于切割通道的交叉点的部分的切割通道。 一旦从半导体晶片切割，半导体芯片就不会产生90度角角。