公开(公告)号：US20190326209A1

公开(公告)日：2019-10-24

申请号：US15959727

申请日：2018-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Xiaoqiang Zhang ,  Haizhou Yin ,  Moosung M. Chae ,  Jinping Liu ,  Hui Zang

IPC: H01L23/528 ,  H01L23/525 ,  H01L21/768

Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.

公开(公告)号：US10453936B2

公开(公告)日：2019-10-22

申请号：US15797837

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Chang Seo Park ,  Shimpei Yamaguchi ,  Tao Han ,  Yong Mo Yang ,  Jinping Liu ,  Hyuck Soo Yang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a sacrificial gate electrode material, performing a first gate-cut etching process to thereby form an opening in the sacrificial gate electrode material and forming an internal sidewall spacer in the opening. In this example, the method also includes, after forming the internal sidewall spacer, performing a second gate-cut etching process through the opening, the second gate-cut etching process being adapted to remove the sacrificial gate electrode material, performing an oxidizing anneal process and forming an insulating material in at least the opening.

公开(公告)号：US10403742B2

公开(公告)日：2019-09-03

申请号：US15712748

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Haiting Wang ,  David P. Brunco ,  Jiehui Shu ,  Shesh Mani Pandey ,  Jinping Liu ,  Scott Beasor

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/10 ,  H01L21/84 ,  H01L27/12

Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.

公开(公告)号：US10008456B1

公开(公告)日：2018-06-26

申请号：US15469983

申请日：2017-03-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tao Han ,  Man Gu ,  Jinping Liu

IPC: H01L23/58 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/60

CPC classification number: H01L21/28141 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/0228 ,  H01L29/6656 ,  H01L2021/6009

Abstract: Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. First and second spacers are formed adjacent to a surface of a device component from respective conformal layers. The first spacer is positioned between the surface of the device component and the second spacer. The second spacer includes a plurality of first lamina and a plurality of second lamina that are arranged in an alternating sequence with the first lamina. The first spacer has a first dielectric constant, and the second spacer has a second dielectric constant that is greater than the first dielectric constant.

公开(公告)号：US09947769B1

公开(公告)日：2018-04-17

申请号：US15363461

申请日：2016-11-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tao Han ,  Zhenyu Hu ,  Jinping Liu ,  Hsien-Ching Lo ,  Jianwei Peng

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/6656 ,  H01L21/0214 ,  H01L21/0228 ,  H01L29/66795 ,  H01L29/785

Abstract: Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer is located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer is located between the second spacer and the vertical sidewall of the gate electrode. The first spacer has a higher dielectric constant than the second spacer. The first spacer has a higher dielectric constant than the third spacer. The third spacer has a lower dielectric constant than the second spacer.

公开(公告)号：US09905472B1

公开(公告)日：2018-02-27

申请号：US15440072

申请日：2017-02-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Jinping Liu ,  Haifeng Sheng

IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L27/088 ,  H01L23/535 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L21/823475 ,  H01L21/0217 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/41725

Abstract: A method of removing the CESL from small canyon TS structures of a MOSFET device while maintaining gate cap height and the resulting device are provided. Embodiments include providing two gates laterally separated over and perpendicular to a fin of a semiconductor device, each gate having sidewall spacers and a nitride cap; forming a conformal SiN CESL on bottom and side surfaces of a trench formed between opposing spacers between the gates; filling the trench with oxide; planarizing the spacers, nitride caps, oxide, and CESL; removing the oxide; forming a topological flat-SiN layer over the spacers, nitride caps, and CESL; removing the topological flat-SiN layer from side and bottom surfaces of the trench; removing the CESL and the topological flat-SiN layer down to a top surface of the spacers; and performing contact metallization.

公开(公告)号：US09882052B2

公开(公告)日：2018-01-30

申请号：US15197892

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert Judson Holt ,  Jinping Liu ,  Jody Fronheiser ,  Bharat Krishnan ,  Churamani Gaire ,  Timothy James McArdle ,  Murat Kerem Akarvardar

IPC: H01L21/335 ,  H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L21/762 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L21/02694 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.

公开(公告)号：US09704746B1

公开(公告)日：2017-07-11

申请号：US15235892

申请日：2016-08-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Jinping Liu ,  Archana Subramaniyan

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L21/02

CPC classification number: H01L21/76802 ,  H01L21/0337 ,  H01L21/31144

Abstract: A method of forming a metallization layer by ASAP is provided. Embodiments include forming an ULK layer; forming a SAC SiN layer over the ULK layer; forming mandrels directly on the SAC SiN layer; cutting the mandrels; selectively etching the SAC SiN layer across the cut mandrels, forming first trenches; filling the first trenches with a metal oxide; forming a conformal metal oxide layer over the cut mandrels, the metal oxide, and the SAC SiN layer; removing horizontal portions of the conformal metal oxide layer over the cut mandrels and the SAC SiN layer; removing the cut mandrels; removing exposed portions of the SAC SiN layer and etching the underlying ULK layer, forming second trenches; and stripping a remainder of the metal oxide, conformal metal oxide layer, and SAC SiN layer.

公开(公告)号：US09589807B1

公开(公告)日：2017-03-07

申请号：US15164146

申请日：2016-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Jinping Liu ,  Huang Liu ,  Yuanfang Lu

IPC: H01L21/283 ,  H01L21/762 ,  H01L21/3213 ,  H01L29/66

CPC classification number: H01L21/283 ,  H01L21/32137 ,  H01L21/76224 ,  H01L21/76837 ,  H01L21/7684 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for eliminating interlayer dielectric (ILD) dishing and controlling gate height uniformity is provided. Embodiments include forming a plurality of polysilicon gates over a substrate, each gate having spacers formed on sides of the polysilicon gates and a nitride cap formed on an upper surface; forming a gapfill material between adjacent polysilicon gates; forming an oxide over the gapfill material between the adjacent polysilicon gates; removing the nitride caps; removing a portion of the oxide between the adjacent polysilicon gates, forming a recess; and forming an ILD cap layer in the recess between the adjacent polysilicon gates.

Abstract translation: 提供消除层间电介质（ILD）凹陷并控制栅极高度均匀性的方法。 实施例包括在衬底上形成多个多晶硅栅极，每个栅极具有形成在多晶硅栅极侧面上的隔离物和形成在上表面上的氮化物盖; 在相邻的多晶硅栅极之间形成间隙填充材料; 在相邻的多晶硅栅极之间的间隙填充材料上形成氧化物; 去除氮化物盖; 去除相邻多晶硅栅极之间的氧化物的一部分，形成凹陷; 以及在相邻的多晶硅栅极之间的凹槽中形成ILD覆盖层。

公开(公告)号：US09478622B2

公开(公告)日：2016-10-25

申请号：US14849335

申请日：2015-09-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Jinping Liu

IPC: H01L29/417 ,  H01L29/40 ,  H01L21/768 ,  H01L29/66 ,  H01L29/49 ,  H01L21/311 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/41791 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/401 ,  H01L29/495 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Embodiments of the present invention provide an improved contact formation process for a finFET. Epitaxial semiconductor regions are formed on the fins. A contact etch stop layer (CESL) is deposited on the epitaxial regions. A nitride-oxide conversion process converts a portion of the nitride CESL into oxide. The oxide-converted portions are removed using a selective etch process, and a fill metal is deposited which is in direct physical contact with the epitaxial regions. Damage, such as gouging, of the epitaxial regions is minimized during this process, resulting in an improved contact for finFETs.

Abstract translation: 本发明的实施例提供了一种用于finFET的改进的接触形成方法。 在翅片上形成外延半导体区域。 接触蚀刻停止层（CESL）沉积在外延区域上。 氮化物 - 氧化物转换处理将氮化物CESL的一部分转化为氧化物。 使用选择性蚀刻工艺去除氧化物转化的部分，并且沉积与外延区域直接物理接触的填充金属。 在该过程期间，使外延区域的损耗（例如气蚀）最小化，导致finFET的接触改善。