中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

58 records (took 0.05 seconds)

    MAGNETO-RESISTIVE MEMORY STRUCTURES WITH IMPROVED SENSING, AND ASSOCIATED SENSING METHODS
    21.
    发明申请
    MAGNETO-RESISTIVE MEMORY STRUCTURES WITH IMPROVED SENSING, AND ASSOCIATED SENSING METHODS 审中-公开

    公开(公告)号：US20190244650A1

    公开(公告)日：2019-08-08

    申请号：US15889369

    申请日：2018-02-06

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Akhilesh Jaiswal ,  Ajey P. Jacob ,  Bipul C. Paul ,  William Taylor ,  Danny Pak-Chum Shum

    IPC: G11C11/16 ,  H01L43/08 ,  H01L27/22

    Abstract: A magneto-resistive memory (MRM) structure includes a source line and a first transistor that includes a source region and a drain region. The source line is electrically connected to the source region of the first transistor. The MRM structure further includes an MRM cell that includes an MRM transistor electrically in series with an MRM magnetic tunnel junction (MTJ). The MRM transistor is electrically connected to the drain region of the first transistor such that the MRM cell is electrically in series with the first transistor. Still further, the MRM structure further includes a voltage amplifier electrically connected to a mid-point node of the first transistor and the MRM transistor, a sense-amplifier electrically connected to the voltage amplifier, and a bit line electrically connected to the MRM MTJ of the MRM cell.

    SILICON NITRIDE GRATING COUPLERS
    22.
    发明申请
    SILICON NITRIDE GRATING COUPLERS 审中-公开

    公开(公告)号：US20190227229A1

    公开(公告)日：2019-07-25

    申请号：US15878025

    申请日：2018-01-23

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ajey P. Jacob ,  Yusheng Bian

    IPC: G02B6/124 ,  G02B6/136 ,  G02B6/132

    Abstract: Grating couplers and methods of fabricating a grating coupler. The grating coupler may include a plurality of grating structures arranged on a substrate and a layer arranged over the grating structures. The grating structures are composed of a first material characterized by a first refractive index with a real part. The layer is composed of a second material characterized by a second refractive index with a real part. The real part of the second refractive index is greater than the real part of the first refractive index of the first material for electromagnetic radiation with a wavelength in a range of 1 micron to 9 microns.

    METHODS OF FORMING STRESSED CHANNEL REGIONS FOR A FINFET SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE
    27.
    发明申请
    METHODS OF FORMING STRESSED CHANNEL REGIONS FOR A FINFET SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE 有权
    形成用于FINFET半导体器件和结果器件的应力通道区域的方法

    公开(公告)号：US20150255542A1

    公开(公告)日：2015-09-10

    申请号：US14200737

    申请日：2014-03-07

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ajey P. Jacob ,  Witold P. Maszara

    IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/1054 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785

    Abstract: One method disclosed includes, among other things, covering the top surface and a portion of the sidewalls of an initial fin structure with etch stop material, forming a sacrificial gate structure around the initial fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, removing the sacrificial gate structure, with the etch stop material in position, to thereby define a replacement gate cavity, performing at least one etching process through the replacement gate cavity to remove a portion of the semiconductor substrate material of the fin structure positioned under the replacement gate cavity that is not covered by the etch stop material so as to thereby define a final fin structure and a channel cavity positioned below the final fin structure and substantially filling the channel cavity with a stressed material.

    Abstract translation: 所公开的一种方法包括用蚀刻停止材料覆盖初始翅片结构的顶表面和侧壁的一部分，围绕初始翅片结构形成牺牲栅极结构，形成邻近牺牲栅极结构的侧壁间隔物， 去除牺牲栅极结构，其中蚀刻停止材料就位，从而限定替换栅极腔，通过替代栅极腔执行至少一个蚀刻工艺，以移除位于替换下方的鳍结构的半导体衬底材料的一部分 门腔不被蚀刻停止材料覆盖，从而限定最终的翅片结构和位于最终翅片结构下方的通道腔，并且用应力材料基本上填充通道腔。

    DEVICE ISOLATION IN FINFET CMOS
    29.
    发明申请
    DEVICE ISOLATION IN FINFET CMOS 有权
    FINFET CMOS器件隔离

    公开(公告)号：US20140353801A1

    公开(公告)日：2014-12-04

    申请号：US13906852

    申请日：2013-05-31

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ajey P. Jacob ,  Murat K. Akarvardar ,  Steven J. Bentley ,  Toshiharu Nagumo ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz

    IPC: H01L21/761 ,  H01L21/762 ,  H01L29/06

    CPC classification number: H01L21/823821 ,  H01L21/02227 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/266 ,  H01L21/3086 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0646 ,  H01L29/66795 ,  H01L29/7851

    Abstract: Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.

    Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离的方法。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 在逆向掺杂层上形成一组替代翅片，该组替换鳍片中的每一个包括高迁移率通道材料（例如，硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和该替代翅片组之间的碳衬垫，以防止载体溢出到置换翅片。

Patent Agency Ranking