公开(公告)号：US09966431B2

公开(公告)日：2018-05-08

申请号：US15078112

申请日：2016-03-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Waikin Li ,  Chengwen Pei ,  Ping-Chuan Wang

IPC: H01L29/06 ,  H01L27/108 ,  H01L29/423 ,  H01L23/522

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  H01L23/5226 ,  H01L27/10805 ,  H01L28/00 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator. At least one bitline extending on a top of the plurality of vertical nanowires and in electrical contact therewith; and at least one wordline formed on vertical sidewalls of the plurality of vertical nanowires and separated therefrom by the dielectric material.

公开(公告)号：US09929290B2

公开(公告)日：2018-03-27

申请号：US15187048

申请日：2016-06-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juntao Li ,  Kangguo Cheng ,  Chengwen Pei ,  Geng Wang ,  Joseph Ervin

IPC: G02B6/12 ,  H01L31/0232 ,  H01L23/48 ,  H01L31/02 ,  G02B6/122 ,  G02B6/42

CPC classification number: H01L31/02327 ,  G02B6/122 ,  G02B6/428 ,  G02B6/43 ,  G02B2006/12061 ,  G02B2006/12123 ,  H01L21/76898 ,  H01L23/481 ,  H01L31/02005

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.

公开(公告)号：US20170338329A1

公开(公告)日：2017-11-23

申请号：US15157868

申请日：2016-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chengwen Pei ,  Xusheng Wu ,  Ziyan Xu

IPC: H01L29/66 ,  H01L21/22 ,  H01L29/207 ,  H01L21/285 ,  H01L21/225 ,  H01L29/78 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/2225 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/31144 ,  H01L29/207 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785

Abstract: Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.

公开(公告)号：US09818652B1

公开(公告)日：2017-11-14

申请号：US15140025

申请日：2016-04-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chengwen Pei ,  Ping-Chuan Wang ,  Kai D. Feng

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/3065 ,  H01L21/28

CPC classification number: H01L21/84 ,  H01L27/1203

Abstract: Structures for a commonly-bodied field-effect transistors and methods of forming such structures. The structure includes a body of semiconductor material defined by a trench isolation region in a semiconductor substrate. The body includes a plurality of first sections, a plurality of second sections, and a third section, the second sections coupling the first sections and the third section. The third section includes a contact region used as a common-body contact for at least the first sections. The first sections and the third section have a first height and the second sections have a second height that is less than the first height.

公开(公告)号：US09595518B1

公开(公告)日：2017-03-14

申请号：US14969449

申请日：2015-12-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony I-Chih Chou ,  Chengwen Pei ,  Edward P. Maciejewski ,  Ning Zhan

IPC: H01L27/06 ,  H01L21/8234 ,  H01L21/265 ,  H01L49/02 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/26513 ,  H01L21/823418 ,  H01L21/823431 ,  H01L28/20 ,  H01L29/0847 ,  H01L29/456 ,  H01L29/7851

Abstract: Fabrication methods and structure include: providing a wafer with at least one fin extended above a substrate in a first region, and at least one fin extended above the substrate in a second region of the wafer; forming a gate structure extending at least partially over the at least one fin to define a semiconductor device region in the first region; implanting a dopant into the at least one fin in the first region and into the at least one fin in the second region of the wafer, where the implanting of the dopant into the at least one fin of the second region modulates a physical property of the at least one fin to define a resistor device region in the second region; and disposing a conductive material at least partially over the at least one fin in the first region and over the at least one fin in the second region of the wafer, in part, to form a source and drain contact in the first region, and a fin-type metal-semiconductor resistor in the second region.

Abstract translation: 制造方法和结构包括：提供具有在第一区域中的衬底上延伸的至少一个翅片的晶片和在晶片的第二区域中在衬底上方延伸的至少一个鳍; 形成至少部分地在所述至少一个翅片上延伸的栅极结构，以在所述第一区域中限定半导体器件区域; 将掺杂剂注入所述第一区域中的所述至少一个翅片并且进入所述晶片的所述第二区域中的所述至少一个翅片，其中所述掺杂剂注入到所述第二区域的所述至少一个翅片中调制所述第二区域的物理性质 至少一个翅片以限定所述第二区域中的电阻器件区域; 以及至少部分地在所述第一区域中的所述至少一个翅片上并且在所述晶片的所述第二区域中的所述至少一个翅片之上至少部分地布置导电材料，以部分地在所述第一区域中形成源极和漏极接触，以及 鳍式金属半导体电阻器。

公开(公告)号：US09557290B2

公开(公告)日：2017-01-31

申请号：US14987329

申请日：2016-01-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

IPC: H01L29/08 ,  G01N27/414 ,  G01N33/487 ,  H01L29/41 ,  H01L21/84 ,  H01L27/12

CPC classification number: G01N27/4145 ,  G01N33/48721 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/413

Abstract: A nanoscale electrode device can be fabricated by forming a pair of semiconductor fins laterally spaced from each other by a uniform distance and formed on a substrate. The pair of semiconductor fins can function as a pair of electrodes that can be biased to detect the leakage current through a nanoscale string to pass therebetween. A nanochannel having a uniform separation distance is formed between the pair of semiconductor fins. The nanochannel may be defined by a gap between a pair of raised active regions formed on the pair of semiconductor fins, or between proximal sidewalls of the pair of semiconductor fins. An opening is formed through the portion of the substrate underlying the region of the nanochannel to enable passing of a nanoscale string.

Abstract translation: 可以通过在基板上形成相互间隔一定距离的一对半导体翅片来制造纳米尺寸的电极装置。 该对半导体散热片可以用作一对电极，该电极可被偏置以检测通过纳米级串的通过的漏电流。 在一对半导体鳍片之间形成具有均匀间隔距离的纳米通道。 纳米通道可以由形成在一对半导体鳍片上的一对凸起的有源区域之间或在该对半导体鳍片的近侧壁之间的间隙限定。 通过在纳米通道的区域下方的衬底的部分形成开口，以使得能够通过纳米级的串。

公开(公告)号：US09379177B2

公开(公告)日：2016-06-28

申请号：US14684533

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/84 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L28/60 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181

Abstract: A deep trench capacitor structure including an SOI substrate comprising an SOI layer, a rare earth oxide layer, and a bulk substrate, the rare earth oxide layer is located below the SOI layer and above the bulk substrate, and the rare earth oxide layer insulates the SOI layer from the bulk substrate, and a deep trench capacitor extending from a top surface of the SOI layer, through the rare earth oxide layer, down to a location within the bulk substrate, the rare earth oxide layer contacts the deep trench capacitor at an interface between the rare earth oxide layer and the bulk substrate forming an incline away from the deep trench capacitor.

Abstract translation: 包括SOI层，稀土氧化物层和体基板的SOI衬底的深沟槽电容器结构，所述稀土氧化物层位于所述SOI层的下方并且位于所述本体衬底的上方，并且所述稀土氧化物层绝缘 SOI层，以及从SOI层的顶表面延伸穿过稀土氧化物层的深沟槽电容器，到达本体衬底内的位置，稀土氧化物层在 稀土氧化物层与本体衬底之间的界面形成远离深沟槽电容器的斜面。

公开(公告)号：US09293520B2

公开(公告)日：2016-03-22

申请号：US13845560

申请日：2013-03-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Geng Wang ,  Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

IPC: H01L21/70 ,  H01L49/02 ,  H01L21/762 ,  H01L21/74 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L28/40 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/0649 ,  H01L29/66181

Abstract: A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.

Abstract translation: 提供一种半导体结构，其包括在基底半导体层上包含外延生长的半导体层的材料堆叠，外延生长的半导体层上的电介质层和存在于电介质层上的上半导体层。 存在从上半导体层通过电介质层延伸到与外延生长的半导体层接触的电容器。 电容器包括存在于沟槽的侧壁上的节点电介质和填充沟槽的至少一部分的上电极。 在从上半导体层通过电介质层和外延半导体层延伸到基底半导体层的掺杂区域的接触沟槽中存在衬底接触。 还提供了通过沟槽的侧壁接触基底半导体层的衬底接触。 还提供了形成上述结构的方法。

公开(公告)号：US09281390B2

公开(公告)日：2016-03-08

申请号：US13964612

申请日：2013-08-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Chandrasekara Kothandaraman ,  Chengwen Pei

IPC: H01L29/786 ,  H01L21/336 ,  H01L29/78 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/792 ,  H01L27/105 ,  H01L21/8234

CPC classification number: H01L29/78 ,  H01L21/28282 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/1052 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

Abstract: A method of fabricating a memory device is provided that may begin with forming a layered gate stack atop a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode atop a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.

Abstract translation: 提供一种制造存储器件的方法，其可以开始于在半导体衬底顶上形成分层栅极堆叠并且图案化停止在层状栅叠层的高k栅极电介质层上的金属电极层，以提供第一金属栅电极和 半导体衬底上的第二金属栅电极。 在下一个处理顺序中，在第一金属栅电极的高k栅介质层的一部分顶上形成至少一个间隔物，其中高k栅极电介质的剩余部分被暴露。 蚀刻高k栅极电介质层的剩余部分以提供具有延伸超过第一金属栅电极的侧壁的部分的第一高k栅极电介质和具有对准边缘的第二高k栅极电介质 到第二金属栅电极的侧壁。

公开(公告)号：US09240406B2

公开(公告)日：2016-01-19

申请号：US14257143

申请日：2014-04-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kai D. Feng ,  Dan Moy ,  Chengwen Pei ,  Robert R. Robison ,  Pinping Sun ,  Richard A. Wachnik ,  Ping-Chuan Wang

IPC: H01L27/07 ,  H01L29/66 ,  H01L29/94

CPC classification number: H01L27/0733 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/11206 ,  H01L29/66181 ,  H01L29/945

Abstract: A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection.

Abstract translation: 电容器结构可以包括多个沟槽电容器的并联连接。 电连接多个沟槽电容器的第一节点以提供电容器结构的第一节点。 多个沟槽电容器的第二节点通过电容器结构的第二节点处的至少一个可编程电连接电连接在一起。 每个可编程电气连接可以包括可编程电熔丝和场效应晶体管中的至少一个，并且可以临时或永久地断开相应的沟槽电容器。 可以通过暂时或永久地编程至少一个可编程电连接来调节电容器结构的总电容。