公开(公告)号：US20210066118A1

公开(公告)日：2021-03-04

申请号：US16553737

申请日：2019-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michel J. Abou-Khalil ,  Aaron Vallett ,  Steven M. Shank ,  Bojidha Babu ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L21/762 ,  H01L21/324 ,  H01L21/265 ,  H01L29/06

Abstract: Structures including electrical isolation and methods associated with forming such structures. A semiconductor layer has a top surface, a polycrystalline region, and a single-crystal region between the polycrystalline region and the top surface. An isolation band is located beneath the single-crystal region. The isolation band contains a first concentration of an n-type dopant and a second concentration of a p-type dopant, and a net difference between the first concentration and the second concentration is within a range of about five percent to about fifteen percent.

公开(公告)号：US10818764B2

公开(公告)日：2020-10-27

申请号：US16520670

申请日：2019-07-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to poly gate extension source to body contact structures and methods of manufacture. The structure includes: a substrate having a doped region; a gate structure over the doped region, the gate structure having a main body and a gate extension region; and a body contact region straddling over the gate extension region and remote from the main body of the gate structure.

公开(公告)号：US20200176589A1

公开(公告)日：2020-06-04

申请号：US16207915

申请日：2018-12-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Mark Goldstein

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/265 ,  H01L21/762 ,  C23C16/40 ,  C23C16/48

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. A semiconductor layer is implanted over a first depth range of an inert gas species to modify the crystal structure of a semiconductor material of the semiconductor layer and form a first modified region. The semiconductor layer is annealed with a first annealing process to convert the semiconductor material within the first modified region to a non-single-crystal layer. The semiconductor layer is also implanted with ions of an element over a second depth range to modify the crystal structure of the semiconductor material of the semiconductor layer and form a second modified region containing a concentration of the element. The semiconductor layer is annealed with a second annealing process to convert the semiconductor material within the second modified region to an insulator layer containing the element.

公开(公告)号：US10665667B2

公开(公告)日：2020-05-26

申请号：US16103357

申请日：2018-08-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anupam Dutta ,  John J. Ellis-Monaghan

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: The present disclosure relates to a semiconductor device, and more particularly, to a junctionless/accumulation mode transistor with dynamic control and method of manufacturing. The circuit includes a channel region and a threshold voltage control on at least one side of the channel region, the threshold voltage control being configured to provide dynamic control of a voltage threshold, leakage current, and breakdown voltage of the circuit, wherein the threshold voltage control is a different dopant or material of a source region and a drain region of the circuit.

公开(公告)号：US20190067905A1

公开(公告)日：2019-02-28

申请号：US15692136

申请日：2017-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John J. Ellis-Monaghan ,  Sebastian Ventrone ,  Vibhor Jain ,  Yves Ngu

IPC: H01S5/062 ,  H01S5/00 ,  H01S5/022 ,  H01S5/026 ,  H01S5/183 ,  H01S5/223 ,  H01S5/22

Abstract: Structures for integrated lasers, systems including integrated lasers, and associated fabrication methods. A ring waveguide and a seed region are arranged interior of the ring waveguide. A laser strip extends across a portion of the ring waveguide. The laser strip has an end contacting the seed region and another opposing end. The laser strip includes a laser medium and a p-n junction capable of generating electromagnetic radiation. The p-n junction of the laser strip is aligned with a portion of the ring waveguide.

公开(公告)号：US20180269295A1

公开(公告)日：2018-09-20

申请号：US15458482

申请日：2017-03-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Alvin J. Joseph ,  John J. Ellis-Monaghan

IPC: H01L29/423 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/06 ,  H01L21/265 ,  H01L29/08 ,  H01L29/78 ,  H01L21/768 ,  H01L23/48 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/42376 ,  H01L21/26513 ,  H01L21/28097 ,  H01L21/28114 ,  H01L21/28167 ,  H01L21/31111 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/4991 ,  H01L29/665 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/78609

Abstract: Device structures for a field-effect transistor and methods for forming a device structure for a field-effect transistor. A first dielectric layer is formed, and a second dielectric layer are formed on the first dielectric layer. An opening is formed that extends vertically through the first and second dielectric layers. After the first opening is formed, the second dielectric layer is laterally recessed relative to the first dielectric layer with a selective etching process, which widens a portion of the opening extending vertically through the second dielectric layer relative to a portion of the opening extending vertically through the first dielectric layer. After the second dielectric layer is laterally recessed, a gate electrode is formed that includes a narrow section in the portion of the opening extending vertically through the first dielectric layer and a wide section in the portion of the opening extending vertically through the second dielectric layer.

公开(公告)号：US20180182778A1

公开(公告)日：2018-06-28

申请号：US15901997

申请日：2018-02-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  Terence B. Hook ,  Kirk D. Peterson

IPC: H01L27/12 ,  H01L29/10 ,  H01L21/66 ,  H01L21/84 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L27/11

CPC classification number: H01L27/1203 ,  H01L21/76283 ,  H01L21/84 ,  H01L22/20 ,  H01L27/11 ,  H01L29/0649 ,  H01L29/1087 ,  H01L29/4908 ,  H01L29/66568 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78654 ,  H01L29/78696

Abstract: A method for fabricating a fully depleted silicon on insulator (FDSOI) device is described. A charge trapping layer in a buried oxide layer is provided on a semiconductor substrate. A backgate well in the semiconductor substrate is provided under the charge trapping layer. A device structure including a gate structure, source and drain regions is disposed over the buried oxide layer. A charge is trapped in the charge trapping layer. The threshold voltage of the device is partially established by the charge trapped in the charge trapping layer. Different aspects of the invention include the structure of the FDSOI device and a method of tuning the charge trapped in the charge trapping layer of the FDSOI device.

公开(公告)号：US20180166536A1

公开(公告)日：2018-06-14

申请号：US15372929

申请日：2016-12-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan

IPC: H01L29/10 ,  H01L23/66 ,  H01L29/06

CPC classification number: H01L29/1083 ,  H01L21/762 ,  H01L21/76283 ,  H01L21/764 ,  H01L21/823481 ,  H01L23/66 ,  H01L25/18 ,  H01L29/0649 ,  H01L29/78 ,  H01L2223/6683

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to active and passive radio frequency (RF) components with deep trench isolation structures and methods of manufacture. The structure includes a bulk high resistivity wafer with a deep trench isolation structure having a depth deeper than a maximum depletion depth at worst case voltage bias difference between devices which are formed on the bulk high resistivity wafer.

公开(公告)号：US09954137B2

公开(公告)日：2018-04-24

申请号：US15594951

申请日：2017-05-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  John C. S. Hall ,  Marwan H. Khater ,  Edward W. Kiewra ,  Steven M. Shank

IPC: H01L21/00 ,  H01L31/20 ,  H01L27/146 ,  H01L31/028 ,  H01L31/0203 ,  H01L21/02

CPC classification number: H01L31/202 ,  H01L21/02667 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14689 ,  H01L27/14692 ,  H01L27/14694 ,  H01L27/14698 ,  H01L31/0203 ,  H01L31/028 ,  H01L31/208

Abstract: Photodetector structures and methods of manufacture are provided. The method includes forming undercuts about detector material formed on a substrate. The method further includes encapsulating the detector to form airgaps from the undercuts. The method further includes annealing the detector material causing expansion of the detector material into the airgaps.

公开(公告)号：US09882081B2

公开(公告)日：2018-01-30

申请号：US15227081

申请日：2016-08-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  John C. S. Hall ,  Marwan H. Khater ,  Edward W. Kiewra ,  Steven M. Shank

IPC: H01L27/144 ,  H01L31/0203 ,  H01L31/0216 ,  H01L31/028 ,  H01L31/105 ,  H01L31/18 ,  H01L31/103 ,  H01L27/146 ,  H01L31/0232

CPC classification number: H01L31/1808 ,  H01L27/1443 ,  H01L27/1446 ,  H01L27/14629 ,  H01L31/0203 ,  H01L31/02161 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/103 ,  H01L31/105 ,  H01L31/1872

Abstract: Disclosed are a method of forming a photodetector and a photodetector structure. In the method, a polycrystalline or amorphous light-absorbing layer is formed on a dielectric layer such that it is in contact with a monocrystalline semiconductor core of an optical waveguide. The light-absorbing layer is then encapsulated in one or more strain-relief layers and a rapid melting growth (RMG) process is performed to crystallize the light-absorbing layer. The strain-relief layer(s) are tuned for controlled strain relief so that, during the RMG process, the light-absorbing layer remains crack-free. The strain-relief layer(s) are then removed and an encapsulation layer is formed over the light-absorbing layer (e.g., filling in surface pits that developed during the RMG process). Subsequently, dopants are implanted through the encapsulation layer to form diffusion regions for PIN diode(s). Since the encapsulation layer is relatively thin, desired dopant profiles can be achieved within the diffusion regions.