公开(公告)号：US20150041905A1

公开(公告)日：2015-02-12

申请号：US13959847

申请日：2013-08-06

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Kisik Choi ,  Su Chen Fan ,  Shom Ponoth

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/28

CPC classification number: H01L27/0922 ,  H01L21/28114 ,  H01L21/823842 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

Abstract: Disclosed herein are illustrative methods and devices that involve forming spacers with internally trimmed internal surfaces to increase the width of the upper portions of a gate cavity. In some embodiments, the internal surface of the spacer has a stepped cross-sectional configuration or a tapered cross-sectional configuration. In one example, a device is disclosed wherein the P-type work function metal for a PMOS device is positioned only within the lateral space defined by the untrimmed internal surfaces of the spacers, while the work function adjusting metal for the NMOS device is positioned laterally between the lateral spaces defined by both the trimmed and untrimmed internal surfaces of the sidewall spacers.

Abstract translation: 这里公开的是说明性方法和装置，其涉及形成具有内部修整的内表面的间隔物，以增加栅腔的上部的宽度。 在一些实施例中，间隔件的内表面具有阶梯形横截面构造或锥形横截面构造。 在一个示例中，公开了一种器件，其中用于PMOS器件的P型功函数金属仅位于由间隔物的未修整内表面限定的横向空间内，而用于NMOS器件的功函数调整金属位于横向 在由侧壁间隔件的修剪和未修整内表面限定的横向空间之间。

公开(公告)号：US20140339629A1

公开(公告)日：2014-11-20

申请号：US13894513

申请日：2013-05-15

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Shom Ponoth ,  David V. Horak ,  Balasubramanian Pranatharthiharan

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66666

Abstract: Embodiments of the invention provide approaches for forming gate and source/drain (S/D) contacts. Specifically, the semiconductor device includes a gate transistor formed over a substrate, a S/D contact formed over a trench-silicide (TS) layer and positioned adjacent the gate transistor, and a gate contact formed over the gate transistor, wherein at least a portion of the gate contact is aligned over the TS layer. This structure enables contact with the TS layer, thereby decreasing the distance between the gate contact and the source/drain, which is desirable for ultra-area-scaling.

Abstract translation: 本发明的实施例提供了用于形成栅极和源极/漏极（S / D）触点的方法。 具体地，半导体器件包括形成在衬底上的栅极晶体管，形成在沟槽硅化物（TS）层上并且邻近栅极晶体管定位的S / D接触，以及形成在栅极晶体管上的栅极接触，其中至少一个 栅极触点的一部分在TS层上对齐。 这种结构使得能够与TS层接触，从而减小栅极接触和源极/漏极之间的距离，这对于超区域缩放是期望的。

公开(公告)号：US20140191319A1

公开(公告)日：2014-07-10

申请号：US13733943

申请日：2013-01-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Kangguo Cheng ,  Shom Ponoth ,  Balasubramanian Pranatharthiharan ,  Theodorus Eduardus Standaert ,  Tenko Yamashita ,  Robert J. Miller

IPC: H01L29/78 ,  H01L21/02

CPC classification number: H01L21/845 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/1211 ,  H01L29/861

Abstract: A diode for integration with finFET devices is disclosed. An in-situ doped epitaxial silicon region is grown on the cathode or anode of the diode to increase the surface area of the junction and overall silicon volume for improved heat dissipation during an ESD event.

Abstract translation: 公开了一种用于与finFET器件集成的二极管。 在二极管的阴极或阳极上生长原位掺杂的外延硅区域，以增加结的表面面积和整体硅体积，以改善ESD事件期间的散热。

公开(公告)号：US20140124840A1

公开(公告)日：2014-05-08

申请号：US13670674

申请日：2012-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

Abstract translation: 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一​​次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。

公开(公告)号：US09953978B2

公开(公告)日：2018-04-24

申请号：US14981574

申请日：2015-12-28

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Kisik Choi ,  Su Chen Fan ,  Shom Ponoth

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/49 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/28114 ,  H01L21/823842 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

Abstract: A transistor device includes a gate structure positioned above a semiconductor substrate, and spaced-apart sidewall spacers positioned above the substrate and adjacent sidewalls of the gate structure. An internal sidewall surface of each of the spaced-apart sidewall spacers includes an upper sidewall surface portion and a lower sidewall surface portion positioned between the upper sidewall surface portion and a surface of the substrate, wherein a first lateral width between first upper ends of the upper sidewall surface portions is greater than a second lateral width between second upper ends of the lower sidewall surface portions.

公开(公告)号：US09711503B2

公开(公告)日：2017-07-18

申请号：US14731569

申请日：2015-06-05

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Shom Ponoth ,  Juntao Li

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L27/085 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L21/823828 ,  H01L27/0207 ,  H01L27/085 ,  H01L27/092 ,  H01L29/0692 ,  H01L29/42372 ,  H01L29/4916 ,  H01L29/66628

Abstract: One method disclosed herein includes, among other things, forming a line-end protection layer in an opening on an entirety of each opposing, spaced-apart first and second end face surfaces of first and second spaced-apart gate electrode structures, respectively, and forming a sidewall spacer adjacent opposing sidewall surfaces of each of the gate electrode structures but not adjacent the opposing first and second end face surfaces having the line-end protection layer positioned thereon.

公开(公告)号：US09332628B2

公开(公告)日：2016-05-03

申请号：US14739703

申请日：2015-06-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H05K1/02 ,  H01L21/768 ,  H05K1/03

CPC classification number: H05K1/0216 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H05K1/0298 ,  H05K1/03 ,  H05K2201/0707 ,  H05K2201/09063

Abstract: A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.

公开(公告)号：US09202879B2

公开(公告)日：2015-12-01

申请号：US13775988

申请日：2013-02-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Charles W. Koburger, III ,  Marc A. Bergendahl ,  David V. Horak ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L21/336 ,  H01L29/40 ,  E21B43/30 ,  E21B47/12

CPC classification number: H01L29/401 ,  E21B43/305 ,  E21B47/122 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211

Abstract: In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics.

Abstract translation: 在替代栅极方案中，在形成栅极电介质层之后，功函数材料层完全填充窄栅极沟槽，同时不填充宽栅极沟槽。 介电材料层在功函数材料层上沉积并平面化，随后凹入以形成覆盖宽栅极沟槽内的功函数材料层的水平部分的介电材料部分。 使用介电材料部分作为蚀刻掩模的一部分来凹入功函数材料层以形成功函数材料部分。 将导电材料沉积并平坦化以形成栅极导体部分，并且沉积和平坦化介电材料以形成栅极盖电介质。

公开(公告)号：US09190487B2

公开(公告)日：2015-11-17

申请号：US14283409

申请日：2014-05-21

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

Abstract translation: 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一​​次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。

公开(公告)号：US20150129970A1

公开(公告)日：2015-05-14

申请号：US14079043

申请日：2013-11-13

Applicant: International Business Machine Corporation ,  GlobalFoundries Inc.

Inventor： Ruilong Xie ,  Shom Ponoth ,  Juntao Li

IPC: H01L29/49 ,  H01L27/085

CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L21/823828 ,  H01L27/0207 ,  H01L27/085 ,  H01L27/092 ,  H01L29/0692 ,  H01L29/42372 ,  H01L29/4916 ,  H01L29/66628

Abstract: One method disclosed herein includes, among other things, forming a line-end protection layer in an opening on an entirety of each opposing, spaced-apart first and second end face surfaces of first and second spaced-apart gate electrode structures, respectively, and forming a sidewall spacer adjacent opposing sidewall surfaces of each of the gate electrode structures but not adjacent the opposing first and second end face surfaces having the line-end protection layer positioned thereon.

Abstract translation: 本文公开的一种方法包括分别在第一和第二间隔开的栅电极结构的每个相对的间隔开的第一和第二端面表面的整个开口中的开口中形成线端保护层，以及 形成邻近每个栅极电极结构的相对侧壁表面的侧壁间隔件，但不邻近具有定位在其上的线端保护层的相对的第一和第二端面表面。