公开(公告)号：US10224276B2

公开(公告)日：2019-03-05

申请号：US15787146

申请日：2017-10-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Robert K. Leidy

IPC: H01L29/40 ,  H01L23/522 ,  H01L23/525 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31

Abstract: Various aspects include an integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.

公开(公告)号：US20170168242A1

公开(公告)日：2017-06-15

申请号：US14966781

申请日：2015-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shawn A. Adderly ,  Samantha D. DiStefano ,  Jeffrey P. Gambino ,  Prakash Periasamy ,  Donald R. Letourneau

IPC: G02B6/30 ,  G02B6/122 ,  G02B6/13 ,  G02B6/136

CPC classification number: G02B6/30 ,  G02B6/122 ,  G02B6/13 ,  G02B6/136

Abstract: The disclosure relates to semiconductor structures and, more particularly, to waveguide structures used in phonotics chip packaging and methods of manufacture. The structure includes: a first die comprising photonics functions including a waveguide structure; a second die bonded to the first die and comprising CMOS logic functions; and an optical fiber optically coupled to the waveguide structure and positioned within a cavity formed in the second die.

公开(公告)号：US09659835B1

公开(公告)日：2017-05-23

申请号：US15094026

申请日：2016-04-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeffrey P. Gambino ,  Richard S. Graf ,  Sundeep Mandal

IPC: H01L27/02 ,  H01L23/36 ,  H01L23/367 ,  G06F17/50

CPC classification number: H01L23/3677 ,  G06F17/505 ,  G06F17/5077 ,  G06F2217/80 ,  H01L27/0207

Abstract: A technique for designing an integrated circuit includes placing standard cells across a first surface of a substrate of an integrated circuit (IC) design. At least two unoccupied regions are located across the first surface that do not include standard cells. Aspect ratios for one or more micro fill vias that can be placed in the at least two unoccupied regions are determined. The one or more micro fill vias are placed in the at least two unoccupied regions. Finally, one or more partial thermal vias are placed from a second surface of the integrated circuit, opposite the first surface, to thermally couple the one or more partial thermal vias to the one or more micro fill vias to create thermal paths from the first surface to the second surface.

公开(公告)号：US09331037B2

公开(公告)日：2016-05-03

申请号：US14886177

申请日：2015-10-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L21/44 ,  H01L21/4763 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/03845 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/11011 ,  H01L2224/1134 ,  H01L2224/11472 ,  H01L2224/11616 ,  H01L2224/1162 ,  H01L2224/1182 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/2064

Abstract: “Thick line dies” that, during manufacture, avoid locating an upstanding edge of a photoresist layer (for example, the edge of a dry film photoresist layer) on top of a “discontinuity.” In this way solder does not flow into the mechanical interface between the photoresist layer and the layer under the photoresist layer in the vicinity of an upstanding edge of the photoresist layer.

Abstract translation: “粗线模具”，在制造过程中，避免在“不连续”的顶部定位光致抗蚀剂层（例如，干膜光致抗蚀剂层的边缘）的直立边缘。这样焊料不会流入机械 光致抗蚀剂层和光致抗蚀剂层下面的层之间在光致抗蚀剂层的直立边缘附近的界面。

公开(公告)号：US20160111352A1

公开(公告)日：2016-04-21

申请号：US14967965

申请日：2015-12-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel J. Couture ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Anthony K. Stamper

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/76834 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02125 ,  H01L2224/0226 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/05442

Abstract: An approach to creating a semiconductor structure for a dielectric layer over a void area includes determining a location of a void area of the topographical semiconductor feature. A second dielectric layer is deposited on a first dielectric layer and a top surface of a topographical semiconductor feature. The second dielectric layer is patterned to one or more portions, wherein at least one portion of the patterned second dielectric layer is over the location of the void area of the topographical semiconductor feature. A first metal layer is deposited over the second dielectric layer, at least one portion of the first dielectric layer, and a portion of the top surface of the topographical semiconductor feature. A chemical mechanical polish of the first metal layer is performed, wherein the chemical mechanical polish reaches the top surface of at least one of the one or more portions of the second dielectric layer.

Abstract translation: 在空隙区域上形成用于介电层的半导体结构的方法包括确定形貌半导体特征的空隙区域的位置。 第二电介质层沉积在第一介电层和地形半导体特征的顶表面上。 将第二介电层图案化成一个或多个部分，其中图案化的第二介电层的至少一部分在形貌半导体特征的空隙区域的位置之上。 第一金属层沉积在第二电介质层上，第一介电层的至少一部分和形貌半导体特征的顶表面的一部分。 执行第一金属层的化学机械抛光，其中化学机械抛光剂到达第二介电层的一个或多个部分中的至少一个的顶表面。

公开(公告)号：US10712498B2

公开(公告)日：2020-07-14

申请号：US16216321

申请日：2018-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Kirk D. Peterson ,  Jed H. Rankin

IPC: G02B27/01 ,  A61B3/113 ,  G02B6/34 ,  G02B6/42 ,  G02F1/29 ,  G02F1/313 ,  G06K9/00 ,  G06K9/62 ,  G02B27/00 ,  G02F1/31 ,  G02B6/122 ,  G02B6/136 ,  G02B6/125 ,  G02B6/132 ,  G02B6/12 ,  G02B1/04

Abstract: Methods and structures for shielding optical waveguides are provided. A method includes forming a first optical waveguide core and forming a second optical waveguide core adjacent to the first optical waveguide core. The method also includes forming an insulator layer over the first optical waveguide core and the second optical waveguide core. The method further includes forming a shielding structure in the insulator layer between the first optical waveguide core and the second optical waveguide core.

公开(公告)号：US10559743B2

公开(公告)日：2020-02-11

申请号：US15690828

申请日：2017-08-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

IPC: H01L41/293 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H03H9/64 ,  G06F17/50 ,  H01L41/08 ,  H01L41/25 ,  H01L23/66 ,  H01L25/16 ,  H01L27/06 ,  H01L49/02

Abstract: A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

公开(公告)号：US10049897B2

公开(公告)日：2018-08-14

申请号：US15421737

申请日：2017-02-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L21/306 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, an interconnect structure can include: a photosensitive polyimide (PSPI) layer including a pedestal portion; a controlled collapse chip connection (C4) bump overlying the pedestal portion of the PSPI layer; a solder overlying the C4 bump and contacting a side of the C4 bump; and an underfill layer abutting the pedestal portion of the PSPI and the C4 bump, wherein the underfill layer and the solder form a first interface separated from the PSPI pedestal.

公开(公告)号：US20180040556A1

公开(公告)日：2018-02-08

申请号：US15787146

申请日：2017-10-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Robert K. Leidy

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Various aspects include an integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.

公开(公告)号：US09715064B1

公开(公告)日：2017-07-25

申请号：US15263817

申请日：2016-09-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeffrey P. Gambino ,  Robert K. Leidy ,  John J. Ellis-Monaghan ,  Brett T. Cucci ,  Jeffrey C. Maling ,  Jessie C. Rosenberg

IPC: G02B6/124 ,  G02B6/34 ,  G02B6/12

CPC classification number: G02B6/124 ,  G02B6/34 ,  G02B2006/12107

Abstract: Disclosed are multi-chip modules (MCMs) that allow for chip-to-chip transmission of light signals. The MCMs can incorporate at least two components, which are attached (e.g., by interconnects). For example, in one MCM disclosed herein, the two components can be an integrated circuit chip and an interposer to which the integrated circuit chip and one or more additional integrated circuit chips are attached by interconnects. In another MCM disclosed herein, the two components can be two integrated circuit chips that are stacked and attached to each other by interconnects. In either case, the two components can each have a waveguide and a grating coupler coupled to one end of the waveguide. The grating couplers on the different components can be approximately vertically aligned, thereby allowing light signals to be transmitted between the waveguides on those different components. Also, disclosed herein are methods of forming such MCMs.