公开(公告)号：US08383507B2

公开(公告)日：2013-02-26

申请号：US13351370

申请日：2012-01-17

申请人： Kaushik Chanda ,  Cathryn J. Christiansen ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Son V. Nguyen ,  Shom Ponoth ,  Hosadurga Shobha

发明人： Kaushik Chanda ,  Cathryn J. Christiansen ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Son V. Nguyen ,  Shom Ponoth ,  Hosadurga Shobha

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal interconnect structure includes at least a pair of metal lines, a cavity therebetween, and a dielectric metal-diffusion barrier layer located on at least one portion of walls of the cavity. After formation of a cavity between the pair of metal lines, the dielectric metal-diffusion barrier layer is formed on the exposed surfaces of the cavity. A dielectric material layer is formed above the pair of metal lines to encapsulate the cavity. The dielectric metal-diffusion barrier layer prevents diffusion of metal and impurities from one metal line to another metal line and vice versa, thereby preventing electrical shorts between the pair of metal lines.

摘要翻译： 金属互连结构包括至少一对金属线，它们之间的腔，以及位于腔的至少一部分壁上的介电金属扩散阻挡层。 在一对金属线之间形成空腔之后，在空腔的暴露表面上形成介电金属扩散阻挡层。 在一对金属线之上形成介电材料层以封装空腔。 电介质金属扩散阻挡层防止金属和杂质从一个金属线扩散到另一个金属线，反之亦然，从而防止一对金属线之间的电短路。

公开(公告)号：US20100187689A1

公开(公告)日：2010-07-29

申请号：US12695515

申请日：2010-01-28

申请人： Deepak Kulkarni ,  Michael W. Lane ,  Satyanarayana V. Nitta ,  Shom Ponoth

发明人： Deepak Kulkarni ,  Michael W. Lane ,  Satyanarayana V. Nitta ,  Shom Ponoth

IPC分类号： H01L23/498 ,  H01L21/78

CPC分类号： H01L23/562 ,  H01L21/563 ,  H01L23/3178 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83365 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/05552

摘要： An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.

摘要翻译： 在无源区域中包括有源区域的无源区域和切割线的集成电路包括钝化层，其在氧化物层上包括外部氮化物层。 该集成电路还包括钝化层下方和被动区域中的裂纹停止点以及有源区域中的焊球。 钝化层在其中形成的沟槽位于比切割线更远离有源区域并且比切割线更靠近有源区的位置，沟槽完全穿过外部氮化物层，并且至少部分地 通过氧化层。

公开(公告)号：US20070048981A1

公开(公告)日：2007-03-01

申请号：US11162219

申请日：2005-09-01

申请人： Griselda Bonilla ,  Richard Conti ,  Timothy Dalton ,  Nicholas Fuller ,  Kelly Malone ,  Satyanarayana Nitta ,  Shom Ponoth

发明人： Griselda Bonilla ,  Richard Conti ,  Timothy Dalton ,  Nicholas Fuller ,  Kelly Malone ,  Satyanarayana Nitta ,  Shom Ponoth

IPC分类号： H01L21/04

CPC分类号： H01L21/31695 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/76826

摘要： A method for protecting a semiconductor device from carbon depletion type damage includes enriching an exposed surface of a porous interlevel dielectric material (ILD) with a carbon based material, and implementing a plasma based operation on the porous ILD material. The enriching of the porous ILD material reduces effects of carbon depletion as a result of the plasma based operation.

摘要翻译： 用于保护半导体器件免受碳耗竭型损伤的方法包括用碳基材料富集多孔层间电介质材料（ILD）的暴露表面，以及对多孔ILD材料实施基于等离子体的操作。 作为基于等离子体的操作的结果，多孔ILD材料的富集减少了碳耗竭的影响。

公开(公告)号：US08440505B2

公开(公告)日：2013-05-14

申请号：US12695515

申请日：2010-01-28

申请人： Deepak Kulkarni ,  Michael W. Lane ,  Satyanarayana V. Nitta ,  Shom Ponoth

发明人： Deepak Kulkarni ,  Michael W. Lane ,  Satyanarayana V. Nitta ,  Shom Ponoth

IPC分类号： H01L21/44

CPC分类号： H01L23/562 ,  H01L21/563 ,  H01L23/3178 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83365 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/05552

摘要： An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.

摘要翻译： 在无源区域中包括有源区域的无源区域和切割线的集成电路包括钝化层，其在氧化物层上包括外部氮化物层。 该集成电路还包括钝化层下方和被动区域中的裂纹停止点以及有源区域中的焊球。 钝化层在其中形成的沟槽位于比切割线更远离有源区域并且比切割线更靠近有源区的位置，沟槽完全穿过外部氮化物层，并且至少部分地 通过氧化层。

公开(公告)号：US20120111825A1

公开(公告)日：2012-05-10

申请号：US13351370

申请日：2012-01-17

申请人： Kaushik Chanda ,  Cathryn J. Christiansen ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Son V. Nguyen ,  Shom Ponoth ,  Hosadurga Shobha

发明人： Kaushik Chanda ,  Cathryn J. Christiansen ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Son V. Nguyen ,  Shom Ponoth ,  Hosadurga Shobha

IPC分类号： B05D5/12 ,  B05D3/10

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal interconnect structure includes at least a pair of metal lines, a cavity therebetween, and a dielectric metal-diffusion barrier layer located on at least one portion of walls of the cavity. After formation of a cavity between the pair of metal lines, the dielectric metal-diffusion barrier layer is formed on the exposed surfaces of the cavity. A dielectric material layer is formed above the pair of metal lines to encapsulate the cavity. The dielectric metal-diffusion barrier layer prevents diffusion of metal and impurities from one metal line to another metal line and vice versa, thereby preventing electrical shorts between the pair of metal lines.

摘要翻译： 金属互连结构包括至少一对金属线，它们之间的腔，以及位于腔的至少一部分壁上的介电金属扩散阻挡层。 在一对金属线之间形成空腔之后，在空腔的暴露表面上形成介电金属扩散阻挡层。 在一对金属线之上形成介电材料层以封装空腔。 电介质金属扩散阻挡层防止金属和杂质从一个金属线扩散到另一个金属线，反之亦然，从而防止一对金属线之间的电短路。

公开(公告)号：US07977032B2

公开(公告)日：2011-07-12

申请号：US10906268

申请日：2005-02-11

申请人： Christos D. Dimitrakopoulos ,  Daniel C. Edelstein ,  Vincent J. McGahay ,  Satyanarayana V. Nitta ,  Kevin S. Petrarca ,  Shom Ponoth ,  Shahab Siddiqui

发明人： Christos D. Dimitrakopoulos ,  Daniel C. Edelstein ,  Vincent J. McGahay ,  Satyanarayana V. Nitta ,  Kevin S. Petrarca ,  Shom Ponoth ,  Shahab Siddiqui

IPC分类号： G03F7/20

CPC分类号： G03F7/2022

摘要： A method of selectively altering material properties of a substrate in one region while making a different alteration of material properties in an adjoining region is provided. The method includes selectively masking a first portion of the substrate during a first exposure and selectively masking a second portion of the substrate during a second exposure. Additionally, a mask may be formed having more than one thickness where each thickness will selectively reduce the amount of energy from a blanket exposure of the substrate thereby allowing a substrate to receive different levels of energy dosage in a single blanket exposure.

摘要翻译： 提供了一种在邻接区域中对材料性质进行不同的改变的同时选择性地改变一个区域中的衬底的材料特性的方法。 该方法包括在第一曝光期间选择性地掩蔽衬底的第一部分，并且在第二次曝光期间选择性地掩蔽衬底的第二部分。 另外，可以形成具有多于一个厚度的掩模，其中每个厚度将选择性地减少来自衬底的覆盖曝光的能量的量，从而允许衬底在单次覆盖曝光中接收不同水平的能量。

公开(公告)号：US20080090402A1

公开(公告)日：2008-04-17

申请号：US11536893

申请日：2006-09-29

申请人： Griselda Bonilla ,  Shyng-Tsong Chen ,  John A. Fitzsimmons ,  Sanjay Mehta ,  Shom Ponoth

发明人： Griselda Bonilla ,  Shyng-Tsong Chen ,  John A. Fitzsimmons ,  Sanjay Mehta ,  Shom Ponoth

IPC分类号： H01L21/44

CPC分类号： H01L21/76825 ,  H01J2237/0812 ,  H01L21/76883

摘要： A method of fabricating and a structure of an integrated circuit (IC) incorporating a porous dielectric layer are disclosed. A metal line is formed in the porous dielectric layer. A gas cluster ion beam process is applied to the porous dielectric layer so that an upper portion of the dielectric layer is densified to be not porous or non-interconnected low porous, while a lower portion of the porous dielectric layer still maintains its ultra-low dielectric constant after the gas cluster ion beam process.

摘要翻译： 公开了一种制造方法和结合有多孔介电层的集成电路（IC）的结构。 在多孔介电层中形成金属线。 将气体簇离子束工艺应用于多孔介电层，使得电介质层的上部被致密化为不是多孔的或不互连的低多孔，而多孔介电层的下部仍保持其超低 气体离子束过程后的介电常数。

公开(公告)号：US20080265377A1

公开(公告)日：2008-10-30

申请号：US11741908

申请日：2007-04-30

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Ponoth ,  Gregory Breyta

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Ponoth ,  Gregory Breyta

IPC分类号： H01L21/311 ,  H01L29/06

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming cavities within a semiconductor device is disclosed. The method comprises depositing an anti-nucleating layer on the interior surface of cavities within an ILD layer of the semiconductor device. This anti-nucleating layer prevents subsequently deposited dielectric layers from forming within the cavities. By preventing the formation of these layers, the capacitance is reduced, thereby resulting in improved semiconductor performance.

摘要翻译： 公开了一种在半导体器件内形成空腔的方法。 该方法包括在半导体器件的ILD层内的空腔的内表面上沉积抗成核层。 该抗成核层防止随后沉积的介电层在空腔内形成。 通过防止这些层的形成，电容减小，从而提高半导体性能。

公开(公告)号：US07790601B1

公开(公告)日：2010-09-07

申请号：US12561651

申请日：2009-09-17

申请人： Samuel S. S. Choi ,  Lawrence A. Clevenger ,  Maxime Darnon ,  Daniel C. Edelstein ,  Satyanarayana Venkata Nitta ,  Shom Ponoth ,  Pak Leung

发明人： Samuel S. S. Choi ,  Lawrence A. Clevenger ,  Maxime Darnon ,  Daniel C. Edelstein ,  Satyanarayana Venkata Nitta ,  Shom Ponoth ,  Pak Leung

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/31111 ,  H01L21/31144

摘要： Disclosed is a process of an integration method to form an air gap in an interconnect. On top of a metal wiring layer on a semiconductor substrate is deposited a dielectric cap layer followed by a sacrificial dielectric layer and pattern transfer layers. A pattern is transferred through the pattern transfer layers, sacrificial dielectric layer, dielectric cap layer and into the metal wiring layer. The presence of the sacrificial dielectric layer aids in controlling the thickness and profile of the dielectric cap layer which in turn affects reliability of the interconnect.

摘要翻译： 公开了一种在互连中形成气隙的积分方法的过程。 在半导体衬底上的金属布线层的顶部上沉积介电覆盖层，接着是牺牲介电层和图案转移层。 图案通过图案转移层，牺牲介电层，电介质盖层转移到金属布线层中。 牺牲介电层的存在有助于控制电介质盖层的厚度和轮廓，这进而影响互连的可靠性。

公开(公告)号：US20120037962A1

公开(公告)日：2012-02-16

申请号：US12854352

申请日：2010-08-11

申请人： Gregory Breyta ,  David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

发明人： Gregory Breyta ,  David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L29/78

CPC分类号： H01L21/7682 ,  H01L21/31144 ,  H01L23/4821 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5329 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of a semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device in order to minimize parasitic capacitances (e.g., contact-to-contact capacitance, contact-to-diffusion region capacitance, gate-to-contact capacitance, gate-to-diffusion region capacitance, etc.). Specifically, the structure can comprise a semiconductor device on a substrate and at least three dielectric layers stacked above the semiconductor device. An air gap is positioned with the second dielectric layer aligned above the semiconductor device and extending vertically from the first dielectric layer to the third dielectric layer. Also disclosed are embodiments of a method of forming such a semiconductor structure using a self-assembly approach.

摘要翻译： 公开了在半导体器件之上的层间电介质中具有接触电平空气间隙的半导体结构的实施例，以便最小化寄生电容（例如，接触 - 接触电容，接触 - 扩散区电容，栅 - 接触电容，栅极到扩散区域电容等）。 具体地，该结构可以包括在衬底上的半导体器件和堆叠在半导体器件上方的至少三个电介质层。 定位气隙，其中第二电介质层在半导体器件上方对齐并从第一介电层垂直延伸到第三介质层。 还公开了使用自组装方法形成这种半导体结构的方法的实施例。