公开(公告)号：US08823179B2

公开(公告)日：2014-09-02

申请号：US12667383

申请日：2008-06-13

申请人： Chia-Lun Tsai ,  Wen-Cheng Chien ,  Po-Han Lee ,  Wei-Ming Chen ,  Chien-Hung Liu ,  Ying-Nan Wen

发明人： Chia-Lun Tsai ,  Wen-Cheng Chien ,  Po-Han Lee ,  Wei-Ming Chen ,  Chien-Hung Liu ,  Ying-Nan Wen

IPC分类号： H01L23/48 ,  H01L27/146 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L24/12 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/05001 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05099

摘要： An embodiment of the present invention provides an electronic device package, which includes a chip having a first surface and an opposite second surface and a trench extending into a body of the chip along a direction from the second surface to the first surface, wherein a bottom portion of the trench includes at least two contact holes.

摘要翻译： 本发明的实施例提供了一种电子器件封装，其包括具有第一表面和相对的第二表面的芯片以及沿着从第二表面到第一表面的方向延伸到芯片的主体中的沟槽，其中底部 沟槽的一部分包括至少两个接触孔。

公开(公告)号：US08723214B2

公开(公告)日：2014-05-13

申请号：US13150034

申请日：2011-06-01

申请人： Wen-Cheng Chien ,  Chia-Lun Tsai

发明人： Wen-Cheng Chien ,  Chia-Lun Tsai

IPC分类号： H01L33/00 ,  H01L23/495 ,  H01L23/10 ,  H01L23/34 ,  H01L27/15

CPC分类号： H01L24/80 ,  H01L24/48 ,  H01L24/49 ,  H01L33/486 ,  H01L33/60 ,  H01L33/62 ,  H01L33/642 ,  H01L33/647 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15156 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A submount and a manufacturing method thereof are provided. The submount, on which at least a semiconductor die is disposed, is mounted on a circuit board. The submount includes a substrate made of a conductive material or a semiconducting material, a plurality of conductive film patterns, and an insulating film pattern. A surface of the substrate includes a die-bonding area and a plurality of conductive areas. The conductive film patterns are individually distributed in the respective conductive areas. The insulating film pattern is disposed between the conductive film pattern and the insulating film pattern, but is not disposed in the die-bonding area. Furthermore, the semiconductor die is disposed in the die-bonding area and is electrically connected with the conductive film patterns. Because the insulating film pattern is not being disposed in the die-bonding area of the submount, the submount structure has improved heat transfer efficiency.

摘要翻译： 提供了一种基座及其制造方法。 至少设有半导体管芯的基座安装在电路板上。 底座包括由导电材料或半导体材料制成的衬底，多个导电膜图案和绝缘膜图案。 基板的表面包括芯片接合区域和多个导电区域。 导电膜图案分别分布在相应的导电区域中。 绝缘膜图案设置在导电膜图案和绝缘膜图案之间，但不设置在芯片接合区域中。 此外，半导体管芯设置在芯片接合区域中并与导电膜图案电连接。 由于绝缘膜图案不设置在基座的芯片接合区域中，所以基座结构具有改善的传热效率。

公开(公告)号：US08432032B2

公开(公告)日：2013-04-30

申请号：US12687093

申请日：2010-01-13

申请人： Chia-Sheng Lin ,  Chia-Lun Tsai ,  Chang-Sheng Hsu ,  Po-Han Lee

发明人： Chia-Sheng Lin ,  Chia-Lun Tsai ,  Chang-Sheng Hsu ,  Po-Han Lee

IPC分类号： H01L23/48

CPC分类号： H01L24/73 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/29 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposite second surface. A through hole is formed on the first surface, extending from the first surface to the second surface. A conductive trace layer is formed on the first surface and in the through hole. A buffer plug is formed in the through hole and a protection layer is formed over the first surface and in the through hole.

摘要翻译： 提供了芯片封装及其制造方法。 芯片封装包括具有第一表面和相对的第二表面的半导体衬底。 在第一表面上形成有从第一表面延伸到第二表面的通孔。 导电迹线层形成在第一表面和通孔中。 在通孔中形成缓冲塞，在第一表面和通孔中形成保护层。

公开(公告)号：US08384222B2

公开(公告)日：2013-02-26

申请号：US13030887

申请日：2011-02-18

申请人： Chia-Lun Tsai ,  Ching-Yu Ni ,  Jack Chen ,  Wen-Cheng Chien

发明人： Chia-Lun Tsai ,  Ching-Yu Ni ,  Jack Chen ,  Wen-Cheng Chien

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.

摘要翻译： 公开了一种半导体器件及其制造方法。 该器件包括半导体管芯，钝化层，布线再分布层（RDL），Ni / Au层和焊料掩模。 半导体管芯包括在其活性表面中暴露的顶部金属。 钝化层覆盖半导体管芯的有源表面，并且包括覆盖顶部金属的贯通钝化开口。 包括Al层的布线RDL覆盖钝化层，并通过钝化开口电连接到顶部金属。 焊接掩模覆盖钝化层和布线RDL，露出布线RDL的端子。

公开(公告)号：US08284296B2

公开(公告)日：2012-10-09

申请号：US12772458

申请日：2010-05-03

申请人： Chan-Min Chou ,  Chia-Lun Tsai ,  Chih-Pin Yen

发明人： Chan-Min Chou ,  Chia-Lun Tsai ,  Chih-Pin Yen

IPC分类号： H04N5/232 ,  H04N5/228 ,  G03B13/00

CPC分类号： H04N5/23212 ,  H04N5/23241

摘要： A continuous focusing method for a digital camera is described, which is applicable to determine whether the digital camera performs a focusing procedure or not when the digital camera switches from a first scene to a second scene in a live view stage. The continuous focusing method includes the following steps. A preview image of a second scene is obtained. A blur detection procedure is performed on the preview image, so as to acquire a corresponding focus value. It is determined whether the focus value exceeds a focusing threshold value or not; if not, a focusing procedure is performed; otherwise, if the focus value is greater than the focusing threshold value, the digital camera still maintains a current focusing focal length, which represents that a focusing focal length of the second scene is the same as that of the first scene.

摘要翻译： 描述了用于数字照相机的连续聚焦方法，其可应用于当数字照相机在实时显示阶段从第一场景切换到第二场景时，确定数字照相机是否执行聚焦程序。 连续聚焦方法包括以下步骤。 获得第二场景的预览图像。 对预览图像执行模糊检测过程，以获得相应的聚焦值。 确定焦点值是否超过聚焦阈值; 如果不是，则进行聚焦过程; 否则，如果聚焦值大于聚焦阈值，则数字照相机仍保持当前聚焦焦距，其表示第二场景的聚焦焦距与第一场景相同。

公开(公告)号：US20110079892A1

公开(公告)日：2011-04-07

申请号：US12896277

申请日：2010-10-01

申请人： Chia-Lun Tsai ,  Tsang-Yu Liu ,  Chia-Ming Cheng

发明人： Chia-Lun Tsai ,  Tsang-Yu Liu ,  Chia-Ming Cheng

IPC分类号： H01L23/528 ,  H01L21/768

CPC分类号： H01L21/78 ,  H01L21/76898 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/023 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/2919 ,  H01L2224/73253 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/05552

摘要： A chip package includes a substrate having a pad region, a device region, and a remained scribe region located at a periphery of the substrate; a signal and an EMI ground pads disposed on the pad region; a first and a second openings penetrating into the substrate to expose the signal and the EMI ground pads, respectively; a first and a second conducting layers located in the first and the second openings and electrically connecting the signal and the EMI ground pads, respectively, wherein the first conducting layer and the signal pad are separated from a periphery of the remained scribe region, and wherein a portion of the second conducting layer and/or the EMI ground pad extend(s) to a periphery of the remained scribe region; and a third conducting layer surrounding the periphery of the remained scribe region to electrically connect the second conducting layer and/or the EMI ground pad.

摘要翻译： 芯片封装包括具有焊盘区域，器件区域和位于衬底周围的残留刻划区域的衬底; 设置在所述焊盘区域上的信号和EMI接地焊盘; 分别穿入基板以暴露信号和EMI接地焊盘的第一和第二开口; 位于所述第一和第二开口中的第一和第二导电层，分别电连接所述信号和所述EMI接地焊盘，其中所述第一导电层和所述信号焊盘与所述残留划线区域的外围分离，并且其中 所述第二导电层和/或所述EMI接地垫的一部分延伸到所述残留划线区域的周边; 以及围绕剩余划线区域的周边的第三导电层，以电连接第二导电层和/或EMI接地垫。

公开(公告)号：US20090289273A1

公开(公告)日：2009-11-26

申请号：US12471255

申请日：2009-05-22

申请人： Chia-Lun Tsai ,  Ching-Yu Ni ,  Wen-Cheng Chien ,  Shang-Yi Wu ,  Cheng-Te Chou

发明人： Chia-Lun Tsai ,  Ching-Yu Ni ,  Wen-Cheng Chien ,  Shang-Yi Wu ,  Cheng-Te Chou

IPC分类号： H01L33/00

CPC分类号： H01L33/385 ,  H01L33/62 ,  H01L33/64 ,  H01L33/642 ,  H01L2924/0002 ,  H01L2924/00

摘要： A light emitting device package structure is described. The light emitting device package structure includes a substrate serving as a carrier supporting a light emitting device chip. The substrate and the light emitting device chip have a chip side and a substrate side separately. A first electrode layer is disposed on a first surface of the light emitting device chip and a second electrode layer is disposed on a second surface of the light emitting device chip, in which the first surface and the second surface are not coplanar. A first conductive trace is electrically connected to the first electrode layer and a second conductive trace is electrically connected to the second electrode layer. At least the first conductive trace or the second conductive trace is formed along the chip side and the substrate side simultaneously.

摘要翻译： 描述了发光器件封装结构。 发光器件封装结构包括用作支撑发光器件芯片的载体的衬底。 基板和发光元件芯片分别具有芯片侧和基板侧。 第一电极层设置在发光器件芯片的第一表面上，并且第二电极层设置在发光器件芯片的第二表面上，其中第一表面和第二表面不是共面的。 第一导电迹线电连接到第一电极层，并且第二导电迹线电连接到第二电极层。 至少第一导电迹线或第二导电迹线同时沿着芯片侧和衬底侧形成。

公开(公告)号：US08541877B2

公开(公告)日：2013-09-24

申请号：US12849089

申请日：2010-08-03

申请人： Chia-Lun Tsai ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

发明人： Chia-Lun Tsai ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

IPC分类号： H01L23/48

CPC分类号： H01L24/20 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83132 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15184 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.

摘要翻译： 本发明提供一种电子器件封装及其制造方法。 电子器件封装包括载体晶片。 具有多个导电焊盘的电子器件芯片设置在载体晶片上。 隔离层压层包括覆盖载体晶片和电子器件芯片的下部第一隔离层和上部第二隔离层。 隔离层压层具有多个开口以露出导电垫。 在隔离层压层和开口中顺应地形成多个再分配图案。 再分布图案分别电连接到导电焊盘。 多个导电凸块分别形成在再分布图案上，电连接到导电焊盘。

公开(公告)号：US08524241B2

公开(公告)日：2013-09-03

申请号：US12669712

申请日：2008-07-18

申请人： Brian Seed ,  Jia Liu Wolfe ,  Chia-Lun Tsai

发明人： Brian Seed ,  Jia Liu Wolfe ,  Chia-Lun Tsai

IPC分类号： C07K19/00 ,  C07K14/28 ,  C12P21/00 ,  C12N15/31 ,  C07H21/04

CPC分类号： C07K14/28

摘要： The invention features recombinant exotoxins from Vibrio cholerae are for the therapeutic treatment of a variety of human diseases, particularly diseases characterized by an abundance or excess of undesired cells.

摘要翻译： 本发明特征在于来自霍乱弧菌的重组外毒素用于治疗各种人类疾病，特别是以不希望的细胞丰度或过量为特征的疾病。

公开(公告)号：US20120091496A1

公开(公告)日：2012-04-19

申请号：US13150034

申请日：2011-06-01

申请人： Wen-Cheng CHIEN ,  Chia-Lun Tsai

发明人： Wen-Cheng CHIEN ,  Chia-Lun Tsai

IPC分类号： H01L33/62

CPC分类号： H01L24/80 ,  H01L24/48 ,  H01L24/49 ,  H01L33/486 ,  H01L33/60 ,  H01L33/62 ,  H01L33/642 ,  H01L33/647 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15156 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A submount and a manufacturing method thereof are provided. The submount, on which at least a semiconductor die is disposed, is mounted on a circuit board. The submount includes a substrate made of a conductive material or a semiconducting material, a plurality of conductive film patterns, and an insulating film pattern. A surface of the substrate includes a die-bonding area and a plurality of conductive areas. The conductive film patterns are individually distributed in the respective conductive areas. The insulating film pattern is disposed between the conductive film pattern and the insulating film pattern, but is not disposed in the die-bonding area. Furthermore, the semiconductor die is disposed in the die-bonding area and is electrically connected with the conductive film patterns. Because the insulating film pattern is not being disposed in the die-bonding area of the submount, the submount structure has improved heat transfer efficiency.

摘要翻译： 提供了一种基座及其制造方法。 至少设有半导体管芯的基座安装在电路板上。 底座包括由导电材料或半导体材料制成的衬底，多个导电膜图案和绝缘膜图案。 基板的表面包括芯片接合区域和多个导电区域。 导电膜图案分别分布在相应的导电区域中。 绝缘膜图案设置在导电膜图案和绝缘膜图案之间，但不设置在芯片接合区域中。 此外，半导体管芯设置在芯片接合区域中并与导电膜图案电连接。 由于绝缘膜图案不设置在基座的芯片接合区域中，所以基座结构具有改善的传热效率。