公开(公告)号：US5483497A

公开(公告)日：1996-01-09

申请号：US277486

申请日：1994-07-19

申请人： Hirohiko Mochizuki ,  Yoshihiro Takemae ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Katsumi Shigenobu

发明人： Hirohiko Mochizuki ,  Yoshihiro Takemae ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Katsumi Shigenobu

IPC分类号： G11C11/41 ,  G06F12/06 ,  G11C8/12 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C7/00

CPC分类号： G06F12/0623 ,  G11C8/12

摘要： A semiconductor memory having a plurality of banks, a first specify unit, and a second specify unit. The first specify unit is used to specify one of the banks by decoding a bank address signal contained in a row address signal. The second specify unit is used to specify one of the banks by decoding the bank address signal contained in the row address signal, according to bank status signals that indicate whether or not each of the banks is activated. Therefore, the semiconductor memory is used for different bank configurations. Namely, with this arrangement, the semiconductor memory is capable of serving as a memory having a smaller number of banks, to thereby improve convenience.

摘要翻译： 具有多个存储体的半导体存储器，第一指定单元和第二指定单元。 第一指定单元用于通过解码包含在行地址信号中的存储体地址信号来指定存储体之一。 第二指定单元用于根据指示每个存储体是否被激活的存储体状态信号对包含在行地址信号中的存储体地址信号进行解码来指定存储区之一。 因此，半导体存储器用于不同的存储体配置。 也就是说，通过这种布置，半导体存储器能够用作具有较少数量的存储体的存储器，从而提高方便性。

公开(公告)号：US6151274A

公开(公告)日：2000-11-21

申请号：US440665

申请日：1999-11-16

申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Yoshinori Okajima

发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Yoshinori Okajima

IPC分类号： G06F13/42 ,  G06F1/10 ,  G06F1/12 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4093 ,  H03K5/00 ,  H03K5/13 ,  H03K5/135 ,  H03L7/00 ,  H03L7/081 ,  H04L7/00 ,  G11C8/00

CPC分类号： H03L7/0805 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/133 ,  H03K5/135 ,  H03L7/00 ,  H03L7/0814 ,  G11C2207/108

摘要： A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.

摘要翻译： 公开了一种用于实现这种系统的系统和半导体器件。 该系统至少使用半导体器件来与外部时钟产生的内部时钟同步地检索输入信号，该输入信号与外部时钟同步地保持有效。 即使在时钟与接收端的信号之间产生相位差的情况下，或者即使在时钟输入电路与接收端的半导体装置中的其他信号输入电路之间产生相位差的情况下，数据 可以高速转移。 在接收端的半导体器件的每个输入电路包括输入定时调整电路，用于调节施加到输入电路的时钟的相位，使得输入电路以有效和稳定的状态检索输入信号。 在输入信号与输入信号和时钟之间的偏差相比较小的情况下，输入定时调整电路被多个输入电路共享。

公开(公告)号：US5537354A

公开(公告)日：1996-07-16

申请号：US357307

申请日：1994-12-14

申请人： Hirohiko Mochizuki ,  Yoshihiro Takemae ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Hiroyoshi Tomita

发明人： Hirohiko Mochizuki ,  Yoshihiro Takemae ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Hiroyoshi Tomita

IPC分类号： G11C11/401 ,  F02B75/02 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C13/00

CPC分类号： G11C7/1072 ,  F02B2075/025

摘要： A method of making an SDRAM (synchronous dynamic random access memory) into either a low-speed type or a high-speed type includes the steps of determining an electrical connection of a predetermined electrode of the SDRAM, and providing the predetermined electrode with a voltage level defined by the electrical connection, the voltage level determining whether the SDRAM is made into the low-speed type or the high speed type, wherein the low-speed type can carry out consecutive writing operations at a low clock rate for two addresses having the same row address, and the high-speed type can carry out simultaneous writing operations at a high clock rate for two addresses having the same row address and consecutive column addresses.

摘要翻译： 将SDRAM（同步动态随机存取存储器）制成低速型或高速型的方法包括以下步骤：确定SDRAM的预定电极的电连接，并为预定电极提供电压 由电气连接限定的电平，电压电平确定SDRAM是低速型还是高速型，其中低速类型可以以低时钟速率对具有 相同的行地址，并且高速类型可以以具有相同行地址和连续列地址的两个地址以高时钟速率执行同时写入操作。

公开(公告)号：US5767712A

公开(公告)日：1998-06-16

申请号：US892066

申请日：1997-07-14

申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Takaaki Suzuki ,  Junji Ogawa ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki ,  Hideaki Kawai

发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Takaaki Suzuki ,  Junji Ogawa ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki ,  Hideaki Kawai

IPC分类号： G06F1/04 ,  G11C7/22 ,  H01L27/02 ,  H03K3/356 ,  H03K5/13 ,  H03K5/1534 ,  H03K5/24 ,  H03L7/00

CPC分类号： G06F1/04 ,  G11C7/22 ,  G11C7/222 ,  H03K3/356113 ,  H03K3/356156 ,  H03K5/133 ,  H03K5/1534 ,  H03K5/249

摘要： A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

摘要翻译： 一种半导体器件包括：单脉冲发生电路，其在第一时钟信号的上升或下降定时产生具有预定脉冲宽度的单触发脉冲;周期时间测量电路，其测量第一时钟信号的周期时间 根据来自单触发脉冲发生电路的单触发脉冲输出，内部时钟发生电路，其基于由循环时间测量电路测量的周期时间和从单次脉冲发生电路输出的单次脉冲产生第二时钟信号; 射击脉冲发生电路。 第二时钟信号具有与第一时钟信号相同的周期时间，并且具有比第一时钟信号高一个特定时间的上升或下降定时，并且通过减去第一时钟的周期时间获得特定时间 信号，以及数据输出电路，其在从第二时钟信号的上升或下降定时之后的预定延迟时间之后输出数据。

公开(公告)号：US4649406A

公开(公告)日：1987-03-10

申请号：US619897

申请日：1984-06-12

申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Kimiaki Sato

发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Kimiaki Sato

IPC分类号： G11C11/4097 ,  H01L27/108 ,  G11C11/40

CPC分类号： G11C11/4097 ,  H01L27/10808

摘要： In a semiconductor memory device having stacked capacitor-type memory cells, the capacitor of each memory cell includes a base electrode, an insulating layer, and a counter electrode. The base electrode of each memory cell is partly superposed without contact on the base electrodes of other adjacent memory cells.

摘要翻译： 在具有层叠电容器型存储单元的半导体存储器件中，每个存储单元的电容器包括基极，绝缘层和对电极。 每个存储单元的基极部分重叠而不与其它相邻存储单元的基极接触。

公开(公告)号：US4641166A

公开(公告)日：1987-02-03

申请号：US560171

申请日：1983-12-12

申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Kimiaki Sato

发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Kimiaki Sato

IPC分类号： G11C11/401 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10808

摘要： In a semiconductor memory device having stacked capacitor-type memory cells, the capacitor of each memory cell comprises an electrode, an insulating layer, and a counter electrode. The electrode is connected electrically to a source or drain region of a transfer transistor and extends over a part of a word line adjacent to another word line serving a gate electrode of the transfer transistor, at which part no memory cell is formed.

摘要翻译： 在具有层叠电容器型存储单元的半导体存储器件中，每个存储单元的电容器包括电极，绝缘层和对电极。 电极电连接到转移晶体管的源极或漏极区域，并且延伸到与传送晶体管的栅电极相连的另一个字线相邻的字线的一部分上，在该部分没有形成存储单元。

公开(公告)号：US4636982A

公开(公告)日：1987-01-13

申请号：US729200

申请日：1985-05-01

申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Kimiaki Sato

发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Kimiaki Sato

IPC分类号： G11C11/401 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4097 ,  H01L29/93 ,  G11C7/00 ,  G11C11/24

CPC分类号： G11C8/12 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4097

摘要： A semiconductor memory device including at least two groups, each of said groups including a plurality of memory cell array blocks. The number of the memory cell array blocks which are activated in one group is made different from the number of memory cell array blocks which are activated in another group by providing a sequential circuit, thus reducing the maximum power consumption.

摘要翻译： 一种包括至少两组的半导体存储器件，每个所述组包括多个存储单元阵列块。 使一组中激活的存储单元阵列块的数量与通过提供顺序电路在另一组中激活的存储单元阵列块的数量不同，从而降低最大功耗。

公开(公告)号：US4511997A

公开(公告)日：1985-04-16

申请号：US439507

申请日：1982-11-05

申请人： Shigeki Nozaki ,  Yoshihiro Takemae ,  Tomio Nakano

发明人： Shigeki Nozaki ,  Yoshihiro Takemae ,  Tomio Nakano

IPC分类号： G11C11/419 ,  G11C11/34 ,  G11C11/401 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/40

CPC分类号： G11C11/4096

摘要： A metal-insulator semiconductor dynamic memory device including sense amplifiers arrayed on a semiconductor substrate and divided into a plurality of sense amplifier groups. Column decoders are provided, one decoder for each sense amplifier group, each sense amplifier group being selected by the column decoder. One or more control signal lines for simultaneously selecting the output signals of at least two sense amplifiers in the sense amplifier group selected by the column decoder, a plurality of data buses for transferring the output signals of at least two sense amplifiers selected by one or more control signal lines, are included in the memory device. All of the sense amplifiers have the control signal lines and the data buses in common.

摘要翻译： 一种金属绝缘体半导体动态存储器件，包括排列在半导体衬底上并分成多个读出放大器组的读出放大器。 提供列解码器，每个读出放大器组的一个解码器，每个读出放大器组由列解码器选择。 一个或多个控制信号线，用于同时选择由列解码器选择的读出放大器组中的至少两个读出放大器的输出信号;多个数据总线，用于传送由一个或多个选择的至少两个读出放大器的输出信号 控制信号线被包括在存储器件中。 所有的读出放大器都具有控制信号线和数据总线。

公开(公告)号：US4486860A

公开(公告)日：1984-12-04

申请号：US392518

申请日：1982-06-28

申请人： Yoshihiro Takemae ,  Tomio Nakano

发明人： Yoshihiro Takemae ,  Tomio Nakano

IPC分类号： G11C11/401 ,  G11C11/406 ,  G11C11/407 ,  G11C11/413 ,  G11C11/40

CPC分类号： G11C11/406 ,  G11C11/407

摘要： In a dynamic random access memory device, the memory cells, sense amplifiers, word drivers, and the like are divided into a plurality of blocks. During the access mode, only one of the blocks in which a desired row exists is driven while, during the refresh mode, all of the blocks are driven.

摘要翻译： 在动态随机存取存储器件中，存储单元，读出放大器，字驱动器等被分成多个块。 在访问模式期间，只有其中存在所需行的块之一被驱动，而在刷新模式期间驱动所有块。

公开(公告)号：US4443714A

公开(公告)日：1984-04-17

申请号：US331476

申请日：1981-12-16

申请人： Tomio Nakano ,  Yoshihiro Takemae

发明人： Tomio Nakano ,  Yoshihiro Takemae

IPC分类号： H03K19/096 ,  G11C11/408 ,  H03K5/02 ,  H03K17/06 ,  H03K17/24 ,  H03K17/687 ,  H03K19/017 ,  H03K19/0185 ,  H03K5/135

CPC分类号： H03K19/01714 ,  G11C11/408 ,  G11C11/4085 ,  H03K19/01728 ,  H03K19/01855 ,  H03K5/023

摘要： A semiconductor circuit, used as a buffer circuit, has an input stage circuit for receiving an input clock signal and an inverted input clock signal, a bootstrap circuit, including a transistor for receiving the output of the input stage circuit and for maintaining the gate voltage of the transistor at a high level during a standby period, and an output circuit, including a transistor which is switched on and off by the output of the bootstrap circuit. The input stage circuit generates an output clock signal. The semiconductor circuit further comprises a circuit for applying a high level clock signal, having the same phase as the inverted clock sigal and a level higher than the level of the sum of a power source upper limit voltage and a transistor threshold voltage, to transistor gates, whereby the voltage of a point charged during the standby period corresponds to the voltage of the power source throughout the standby period. Thus, delay in the output clock signal, which is the cause of fluctuation of the voltage of the power supply during the standby period, is reduced and high speed access time in the dynamic memory device is accomplished.

摘要翻译： 用作缓冲电路的半导体电路具有用于接收输入时钟信号和反相输入时钟信号的输入级电路，自举电路，包括用于接收输入级电路的输出并保持栅极电压的晶体管 的晶体管在待机期间处于高电平;以及输出电路，包括由所述自举电路的输出导通和截止的晶体管。 输入级电路产生输出时钟信号。 半导体电路还包括用于施加与反相时钟信号具有相同相位并且高于电源上限电压和晶体管阈值电压之和的电平的高电平时钟信号的电路到晶体管栅极 由此，在待机期间充电的点的电压对应于整个等待期间电源的电压。 因此，在待机期间电源的电压波动的原因的输出时钟信号的延迟减小，并且动态存储装置中的高速存取时间得以实现。