公开(公告)号：US20190295951A1

公开(公告)日：2019-09-26

申请号：US15934343

申请日：2018-03-23

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Robert MAY ,  Sameer PAITAL ,  Bai NIE ,  Jesse JONES ,  Chung Kwang Christopher TAN

IPC: H01L23/538 ,  H01L23/522 ,  H01L23/00

Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.

公开(公告)号：US20190169020A1

公开(公告)日：2019-06-06

申请号：US15832223

申请日：2017-12-05

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Kristof DARMAWIKARTA ,  Robert A. MAY ,  Changhua LIU ,  Hiroki TANAKA ,  Feras EID

IPC: B81B7/02 ,  B81C1/00 ,  H01L23/498

Abstract: A package substrate is provided which comprises: one or more first conductive contacts on a first surface; one or more second conductive contacts on a second surface opposite the first surface; a dielectric layer between the first and the second surfaces; and an embedded sensing or actuating element on the dielectric layer conductively coupled with one of the first conductive contacts, wherein the embedded sensing or actuating element comprises a fixed metal layer in the dielectric layer and a flexible metal layer suspended over the fixed metal layer by one or more metal supports on the dielectric layer. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240243066A1

公开(公告)日：2024-07-18

申请号：US18622511

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Robert MAY ,  Sameer PAITAL ,  Bai NIE ,  Jesse JONES ,  Chung Kwang Christopher TAN

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/538 ,  H01L23/5226 ,  H01L23/5381 ,  H01L23/5385 ,  H01L24/82 ,  H01L2224/12105

Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.

公开(公告)号：US20240105580A1

公开(公告)日：2024-03-28

申请号：US17953213

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Kyle MCELHINNY ,  Hiroki TANAKA

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L23/15

CPC classification number: H01L23/49866 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/15 ,  H01L23/49838

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a core, and a pad over the core. In an embodiment, a shell is around the core, and a surface finish is over the shell. In an embodiment, the electronic package further comprises a solder resist over the pad, where an opening is formed through the solder resist to expose the surface finish.

公开(公告)号：US20240097079A1

公开(公告)日：2024-03-21

申请号：US17949857

申请日：2022-09-21

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Khaled AHMED ,  Srinivas V. PIETAMBARAM ,  Hiroki TANAKA ,  Paul WEST ,  Kristof DARMAWIKARTA ,  Gang DUAN ,  Jeremy D. ECTON ,  Suddhasattwa NAD

IPC: H01L33/48 ,  H01L25/075 ,  H01L33/00 ,  H01L33/32 ,  H01L33/62

CPC classification number: H01L33/486 ,  H01L25/0753 ,  H01L33/0075 ,  H01L33/32 ,  H01L33/62 ,  H01L2933/0066

Abstract: Integrated circuit (IC) packages are disclosed. In some embodiments, an IC package includes a glass substrate, a micro light emitting diode (LED), a semiconductor die, one or more through glass vias (TGVs) and a package substrate. The micro LED is positioned over the glass substrate. The TGVs are integrated into the glass substrate and connect the micro LED to the semiconductor die. The semiconductor die is connected to the package substrate to receive external signals when connected to a motherboard.

公开(公告)号：US20240087971A1

公开(公告)日：2024-03-14

申请号：US17943915

申请日：2022-09-13

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Gang DUAN ,  Srinivas V. PIETAMBARAM ,  Kristof DARMAWIKARTA ,  Jeremy D. ECTON ,  Suddhasattwa NAD ,  Hiroki TANAKA ,  Pooya TADAYON

IPC: H01L23/15 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/15 ,  H01L23/5381 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments disclosed herein include interposers and methods of forming interposers. In an embodiment, an interposer comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the interposer further comprises a cavity into the first surface of the substrate, a via through the substrate below the cavity, a first pad in the cavity over the via, and a second pad on the second surface of the substrate under the via.

公开(公告)号：US20230420357A1

公开(公告)日：2023-12-28

申请号：US17848624

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Sameer PAITAL

IPC: H01L23/498 ,  H01L21/02 ,  H01L21/48

CPC classification number: H01L23/49894 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L21/0217 ,  H01L21/486 ,  H01L24/16

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to forming an LGA pad on a side of a substrate, with a layer of silicon nitride between the LGA pad and a dielectric layer of the substrate. The LGA pad may have a reduced footprint, or a reduced lateral dimension with respect to a plane of the substrate, as compared to legacy LGA pads to reduce insertion loss by reducing the resulting capacitance between the reduced LGA footprint and metal routings within the substrate. The layer of silicon nitride may provide additional mechanical support for the reduced footprint. Other embodiments may be described and/or claimed.

公开(公告)号：US20230197770A1

公开(公告)日：2023-06-22

申请号：US17559847

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Hiroki TANAKA ,  Kristof DARMAWIKARTA

IPC: H01L49/02 ,  H01L23/498 ,  H01G4/33 ,  H01G4/08 ,  H01G4/38

CPC classification number: H01L28/90 ,  H01L23/49822 ,  H01G4/33 ,  H01G4/08 ,  H01G4/38

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to electrically coupled trench capacitors within a substrate. The substrate may be part of an interposer, such as a glass interposer, where the trench capacitors deliver a high capacitance density close to one or more dies that are attached to a surface of the substrate. Portions of the trench capacitor may be a thin film capacitor at a surface of the substrate. The trenches extend from a first side of the substrate toward a second side of the substrate opposite the first side. Other embodiments may be described and/or claimed.

公开(公告)号：US20210305668A1

公开(公告)日：2021-09-30

申请号：US17344715

申请日：2021-06-10

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Jeremy D. ECTON ,  Aleksandar ALEKSOV ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Dilan SENEVIRATNE

IPC: H01P1/208 ,  H01L23/66 ,  H01P7/10 ,  H01P3/16 ,  H01L21/768 ,  H01P11/00 ,  H01L21/288 ,  H01P1/20

Abstract: A method of fabricating an RF filter on a semiconductor package comprises forming a first dielectric buildup film. A second dielectric buildup film is formed over the first dielectric buildup film, the second dielectric buildup film comprising a dielectric material that contains a metallization catalyst, wherein the dielectric material comprises one of an epoxy-polymer blend dielectric material, silicon dioxide and silicon nitride, and a low-k dielectric. A trench is formed in the second dielectric buildup film with laser ablation, wherein the laser ablation selectively activates sidewalls of the trench for electroless metal deposition. A metal selectively is plated to sidewalls of the trench based at least in part on the metallization catalyst and immersion in an electroless solution. A low-loss buildup film is formed over the metal that substantially fills the trench.

公开(公告)号：US20200312771A1

公开(公告)日：2020-10-01

申请号：US16366661

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Bai NIE ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Jesse JONES ,  Yosuke KANAOKA ,  Hongxia FENG ,  Dingying XU ,  Rahul MANEPALLI ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Meizi JIAO ,  Chong ZHANG ,  Matthew TINGEY ,  Jung Kyu HAN ,  Haobo CHEN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.