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    ARCHITECTURE FOR REDUCTION OF RF INTERFERENCE ON CLOCK CIRCUITS
    23.
    发明申请
    ARCHITECTURE FOR REDUCTION OF RF INTERFERENCE ON CLOCK CIRCUITS 有权

    公开(公告)号：US20250007501A1

    公开(公告)日：2025-01-02

    申请号：US18214885

    申请日：2023-06-27

    Applicant: Intel Corporation

    Inventor： Eduardo Alban ,  Hao Luo ,  Nasser A. Kurd ,  Kedar Mangrulkar ,  Mohamed A. Abdelmoneum ,  Brent R. Carlton

    IPC: H03K5/1252 ,  G06F1/06 ,  H03B5/36

    Abstract: An apparatus includes an oscillator circuit and a low-pass filter circuit coupled to an output terminal of the oscillator circuit. The apparatus further includes a first digital signal generator coupled to at least one of an output terminal of the low-pass filter circuit and the output terminal of the oscillator circuit and a second digital signal generator coupled to at least one of the output terminal of the low-pass filter circuit and the output terminal of the oscillator circuit. The second digital signal generator generates a second digital clock signal based on a non-differential signal output of the oscillator circuit. The apparatus further includes a radio frequency interference (RFI) detection circuit coupled to the first digital signal generator and the second digital signal generator. The RFI detection circuit detects RFI associated with the non-differential signal output of the oscillator circuit.

    CLOCK GLITCH MITIGATION APPARATUS AND METHOD
    27.
    发明申请
    CLOCK GLITCH MITIGATION APPARATUS AND METHOD 审中-公开

    公开(公告)号：US20200285267A1

    公开(公告)日：2020-09-10

    申请号：US16292204

    申请日：2019-03-04

    Applicant: Intel Corporation

    Inventor： Mohamed A. Abdelmoneum ,  Nasser A. Kurd ,  Thripthi Hegde

    IPC: G06F1/08 ,  G06F9/448 ,  G06F1/14

    Abstract: An apparatus and method to protect unauthorized change to a reference clock for a processor. The apparatus comprises: a first oscillator to generate a first clock; a second oscillator to generate a second clock; a third oscillator to generate a third clock; a first counter to count frequency of the first clock with respect to a fourth clock; a second counter to count frequency of the second clock with respect to the fourth clock; a third counter to count frequency of the third clock with respect to the fourth clock; and a circuitry to compare frequencies of the first, second, and third clocks with one another. The oscillators can be embedded in an interposer or package. These oscillators include one or more of: LC oscillator, micro electro-mechanical system (MEMs) based resonator, or ring oscillator.

    DATA AND CLOCK SYNCHRONIZATION AND VARIATION COMPENSATION APPARATUS AND METHOD
    29.
    发明申请
    DATA AND CLOCK SYNCHRONIZATION AND VARIATION COMPENSATION APPARATUS AND METHOD 审中-公开

    公开(公告)号：US20200143853A1

    公开(公告)日：2020-05-07

    申请号：US16178346

    申请日：2018-11-01

    Applicant: Intel Corporation

    Inventor： Navindra Navaratnam ,  Nasser A. Kurd ,  Bee Min Teng ,  Raymond Chong ,  Nasirul I. Chowdhury ,  Ali M. El-Husseini

    IPC: G11C7/22 ,  H03K5/135 ,  G11C7/10 ,  H01L25/18

    Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.

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