公开(公告)号：US20180095802A1

公开(公告)日：2018-04-05

申请号：US15283006

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Hang T. Nguyen ,  Gordon McFadden ,  Pradeepsunder Ganesh ,  Stephen Thomas Palermo ,  Travis J. White ,  Ashok Raj ,  Vivek Garg ,  Dhruv Singh

IPC: G06F9/50

CPC classification number: G06F9/5044 ,  G06F9/5094 ,  Y02D10/22

Abstract: In one embodiment, a method comprises determining, at a plurality of instances in time, a value of at least one stress characteristic of a hardware resource; determining an accumulated stress value of the hardware resource, the accumulated stress value comprising the sum of a plurality of incremental stress values, an incremental stress value determined based on the value of the at least one stress characteristic at a particular instance in time; and generating a first stress indicator in response to a determination that the accumulated stress value of the hardware resource is greater than a first threshold stress value associated with the hardware resource.

公开(公告)号：US09910470B2

公开(公告)日：2018-03-06

申请号：US14970747

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Vivek Garg ,  Alexander Gendler ,  Arvind Raman ,  Ashish V. Choubal ,  Krishnakanth V. Sistla ,  Dean Mulla ,  Eric J. Dehaemer ,  Rahul Agrawal ,  Guy G. Sotomayor

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/26 ,  G06F1/3243 ,  Y02D10/152

Abstract: In one embodiment, a processor includes cores to execute instructions. At least some of the cores include a telemetry data control logic to send a first telemetry data packet to a power controller according to a stagger schedule to prevent data collisions, and a global alignment counter to count a stagger alignment period. Other embodiments are described and claimed.

公开(公告)号：US20170285700A1

公开(公告)日：2017-10-05

申请号：US15086456

申请日：2016-03-31

Applicant: INTEL CORPORATION

Inventor： Daniel G. Cartagena ,  Corey D. Gough ,  Vivek Garg ,  Nikhil Gupta

IPC: G06F1/20 ,  G06F1/30 ,  G06F1/28

CPC classification number: G06F1/206 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

Abstract: A dynamic adjustment of core power can reduce thermal margin between thermal design power (TDP) and an allowable thermal load. For example, by focusing directly on the core temperatures explicitly, a per-core closed loop temperature controller (pCLTC) can remove conservatism induced by the power level 1 policy (PL1, a policy which defines frequency and/or power for the processor under sustained load) thereby allowing for increased processor performance when there exists margin in the thermal system.

公开(公告)号：US20160170478A1

公开(公告)日：2016-06-16

申请号：US15048055

申请日：2016-02-19

Applicant: Intel Corporation

Inventor： Malini K. Bhandaru ,  Eric J. Dehaemer ,  Scott P. Bobholz ,  Raghunandan Makaram ,  Vivek Garg

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

公开(公告)号：US09268393B2

公开(公告)日：2016-02-23

申请号：US13997295

申请日：2012-11-30

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth Sistla ,  Martin T. Rowland ,  Brian J. Griffith ,  Viktor D. Vogman ,  Joseph R. Doucette ,  Eric J. Dehaemer ,  Vivek Garg ,  Chris Poirier ,  Jeremy J. Shrall ,  Avinash N. Ananthakrishnan ,  Stephen H. Gunther

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/06 ,  G06F9/45

CPC classification number: G06F1/3234 ,  G06F1/06 ,  G06F1/324 ,  G06F8/4432 ,  Y02D10/126

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个核心，每个核心各自独立地执行指令，多个图形引擎各自独立地执行图形操作; 以及功率控制单元，其耦合到所述多个核以控制所述处理器的功率消耗，其中所述功率控制单元包括功率偏移控制逻辑，以将所述处理器的功率消耗水平限制在高于限定功率极限以上 工作周期的占空比部分。 描述和要求保护其他实施例。

公开(公告)号：US11543878B2

公开(公告)日：2023-01-03

申请号：US17042804

申请日：2018-05-01

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Eric Dehaemer ,  Alexander Gendler ,  Nadav Shulman ,  Krishnakanth Sistla ,  Nir Rosenzweig ,  Ankush Varma ,  Ariel Szapiro ,  Arye Albahari ,  Ido Melamed ,  Nir Misgav ,  Vivek Garg ,  Nimrod Angel ,  Adwait Purandare ,  Elkana Korem

IPC: G06F1/32 ,  G06F9/4401 ,  G06F1/329 ,  G06F1/3206 ,  G06F9/30 ,  G06F9/48

Abstract: A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

公开(公告)号：US20220343579A1

公开(公告)日：2022-10-27

申请号：US17719089

申请日：2022-04-12

Applicant: Intel Corporation

Inventor： Ankur Shah ,  Matthew Callaway ,  Vivek Garg ,  Rajeev K. Nalawadi ,  James Varga

IPC: G06T15/00 ,  G06F9/455 ,  G06F9/48 ,  G06F9/50 ,  G06F1/28

Abstract: Apparatus and method for processing virtual graphics processor telemetry data based on quanta. For example, one embodiment of a graphics processing apparatus comprises virtualization control circuitry to virtualize graphics processing resources of one or more graphics processing units (GPU), wherein one or more virtual machines (VMs) are to be provided with controlled access to the graphics processing resources in accordance with a current graphics virtualization configuration specified, at least in part, in one or more virtualization control registers of the virtualization control circuitry; a scheduler to schedule each VM for processing by the graphics processing resources in accordance with the graphics virtualization configuration, the scheduler to generate a VM switch event responsive to each VM being scheduled for processing on the graphics processing resources; power management circuitry to collect telemetry data associated with VMs which have temporarily completed processing on the graphics processing resources and to forward the telemetry data to a telemetry data aggregator, the telemetry data aggregator to combine telemetry data collected for each VM over a period of time and to store per-VM telemetry data in a data repository accessible by a virtualization management application.

公开(公告)号：US20220129031A1

公开(公告)日：2022-04-28

申请号：US17520296

申请日：2021-11-05

Applicant: Intel Corporation

Inventor： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris MacNamara ,  John J. Browne ,  Ripan Das

IPC: G06F1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455 ,  G06F1/324

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US20220100247A1

公开(公告)日：2022-03-31

申请号：US17033753

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Vivek Garg ,  Ankush Varma ,  Krishnakanth Sistla ,  Nikhil Gupta ,  Nikethan Shivanand Baligar ,  Stephen Wang ,  Nilanjan Palit ,  Timothy Kam ,  Adwait Purandare ,  Ujjwal Gupta ,  Stanley Chen ,  Dorit Shapira ,  Shruthi Venugopal ,  Suresh Chemudupati ,  Rupal Parikh ,  Eric Dehaemer ,  Pavithra Sampath ,  Phani Kumar Kandula ,  Yogesh Bansal ,  Dean Mulla ,  Michael Tulanowski ,  Stephen Haake ,  Andrew Herdrich ,  Ripan Das

IPC: G06F1/28 ,  G06F1/30 ,  G06F13/20

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

公开(公告)号：US11157064B2

公开(公告)日：2021-10-26

申请号：US15719276

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Bharat S. Pillilli ,  Eswaramoorthi Nallusamy ,  Ramamurthy Krithivas ,  Vivek Garg ,  Venkatesh Ramamurthy

IPC: G06F1/3287 ,  G06F1/28 ,  G06F1/26

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to send a power operation initiation indication to the accelerator device via the subset of the plurality of interconnects, the power operation initiation indication to indicate a power operation to be performed on one or more infrastructure devices, receive a response the accelerator device, the response to indicate to the processor that the accelerator is ready for the power operation, and ucause the power operation to be performed on the accelerator device, the power operation to enable or disable power for the one or more of the infrastructure devices.