公开(公告)号：US10199372B2

公开(公告)日：2019-02-05

申请号：US15631006

申请日：2017-06-23

Applicant: Infineon Technologies AG

Inventor： Ingo Muri ,  Iris Moder ,  Oliver Hellmund ,  Johannes Baumgartl ,  Annette Saenger ,  Barbara Eichinger ,  Doris Sommer ,  Jacob Tillmann Ludwig

IPC: H01L27/108 ,  H01L29/94 ,  H01L29/76 ,  H01L27/06 ,  H01L23/48 ,  H01L21/768

Abstract: An integrated circuit device including a chip die having a first area with a first thickness surrounding a second area with a second thickness, the first thickness is greater than the second thickness, the chip die having a front-side and a back-side, at least one passive electrical component provided at least one of in or over the chip die in the first area on the front-side, and at least one active electrical component provided at least one of in or over the chip die in the second area on the front-side.

公开(公告)号：US20180233399A1

公开(公告)日：2018-08-16

申请号：US15951995

申请日：2018-04-12

Applicant: Infineon Technologies AG

Inventor： Oliver Hellmund ,  Ingo Muri ,  Johannes Baumgartl ,  Iris Moder ,  Thomas Christian Neidhart ,  Hans-Joachim Schulze

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423 ,  H01L21/3105

Abstract: A semiconductor device includes a trench extending through a semiconductor substrate and an epitaxial layer disposed over a first side of the semiconductor substrate. The epitaxial layer partially fills a portion of the trench. The semiconductor device further includes a back side metal layer disposed over a second side of the semiconductor substrate. The back side metal layer extends into the trench and fills the remaining portion of the trench. The epitaxial layer partially filling the trench contacts the back side metal layer filling the remaining portion within the trench.

公开(公告)号：US09960076B2

公开(公告)日：2018-05-01

申请号：US15229985

申请日：2016-08-05

Applicant: Infineon Technologies AG

Inventor： Oliver Hellmund ,  Ingo Muri ,  Johannes Baumgartl ,  Iris Moder ,  Thomas Christian Neidhart ,  Hans-Joachim Schulze

IPC: H01L29/772 ,  H01L21/762 ,  H01L21/311 ,  H01L21/306 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/3105

CPC classification number: H01L21/76248 ,  H01L21/28 ,  H01L21/30608 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76272 ,  H01L21/76283 ,  H01L21/764 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of fabricating a semiconductor device includes forming trenches filled with a sacrificial material. The trenches extend into a semiconductor substrate from a first side. An epitaxial layer is formed over the first side of the semiconductor substrate and the trenches. From a second side of the semiconductor substrate opposite to the first side, the sacrificial material in the trenches is removed. The trenches are filled with a conductive material.

公开(公告)号：US09862037B2

公开(公告)日：2018-01-09

申请号：US15065914

申请日：2016-03-10

Applicant: Infineon Technologies AG

Inventor： Ingo Muri ,  Alexander Binter ,  Bernhard Goller ,  Christian Grindling

IPC: B23C3/13 ,  B23Q3/08 ,  H01L21/683 ,  H01L21/67 ,  H01L21/304

CPC classification number: B23C3/13 ,  B23Q3/088 ,  H01L21/304 ,  H01L21/67092 ,  H01L21/6838 ,  H01L21/6875 ,  H01L21/68757 ,  Y10T279/11 ,  Y10T409/3042

Abstract: According to various embodiments, a workpiece planarization arrangement may include: a chuck including a support carrier; and a workpiece-support replaceably mounted on the support carrier; and a planarization tool configured to planarize the at least one portion of the workpiece-support and to planarize one or more workpieces on the at least one portion of the workpiece-support.

公开(公告)号：US09627209B2

公开(公告)日：2017-04-18

申请号：US15049192

申请日：2016-02-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Hans-Joachim Schulze ,  Ingo Muri ,  Friedrich Kroener ,  Werner Schustereder

IPC: H01L21/322 ,  H01L29/868 ,  H01L21/265 ,  H01L21/263 ,  H01L21/324 ,  H01L21/3063

CPC classification number: H01L21/26513 ,  H01L21/263 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/3063 ,  H01L21/3242

Abstract: A method for producing a semiconductor is disclosed, the method having: providing a semiconductor body having a first side and a second side; forming an n-doped zone in the semiconductor body by a first implantation into the semiconductor body via the first side to a first depth location of the semiconductor body; and forming a p-doped zone in the semiconductor body by a second implantation into the semiconductor body via the second side to a second depth location of the semiconductor body, a pn-junction forming between said n-doped zone and said p-doped zone in the semiconductor body.

公开(公告)号：US20210265468A1

公开(公告)日：2021-08-26

申请号：US17235989

申请日：2021-04-21

Applicant: Infineon Technologies AG

Inventor： Ingo Muri ,  Johannes Konrad Baumgartl ,  Oliver Hellmund ,  Jacob Tillmann Ludwig ,  Iris Moder ,  Thomas Neidhart ,  Gerhard Schmidt ,  Hans-Joachim Schulze

IPC: H01L29/36 ,  H01L21/223 ,  H01L21/02 ,  H01L21/225 ,  H01L29/167 ,  H01L21/265

Abstract: A semiconductor device includes a semiconductor substrate having a first dopant and a second dopant. A covalent atomic radius of a material of the semiconductor substrate is i) larger than a covalent atomic radius of the first dopant and smaller than a covalent atomic radius of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than the covalent atomic radius of the second dopant. The semiconductor device further includes a semiconductor layer on the semiconductor substrate and semiconductor device elements in the semiconductor layer. A vertical concentration profile of the first dopant decreases along at least 80% of a distance between an interface of the semiconductor substrate and the semiconductor layer to a surface of the semiconductor substrate opposite to the interface.

公开(公告)号：US11038028B2

公开(公告)日：2021-06-15

申请号：US16406773

申请日：2019-05-08

Applicant: Infineon Technologies AG

Inventor： Ingo Muri ,  Johannes Konrad Baumgartl ,  Oliver Hellmund ,  Jacob Tillmann Ludwig ,  Iris Moder ,  Thomas Christian Neidhart ,  Gerhard Schmidt ,  Hans-Joachim Schulze

IPC: H01L29/36 ,  H01L21/223 ,  H01L21/02 ,  H01L21/225 ,  H01L29/167 ,  H01L21/265

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having opposing first and second main surfaces and first and second dopants. A covalent atomic radius of a material of the substrate is i) larger than a covalent atomic radius of the first dopant and smaller than that of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than that of the second dopant. A vertical extension of the first dopant into the substrate from the first main surface ends at a bottom of a substrate portion at a first vertical distance to the first main surface. The method further includes forming a semiconductor layer on the first main surface, forming semiconductor device elements in the semiconductor layer, and reducing a thickness of the substrate by removing material from the second main surface at least up to the substrate portion.

公开(公告)号：US11011409B2

公开(公告)日：2021-05-18

申请号：US16695999

申请日：2019-11-26

Applicant: Infineon Technologies AG

Inventor： Oliver Hellmund ,  Ingo Muri ,  Johannes Baumgartl ,  Iris Moder ,  Thomas Christian Neidhart ,  Hans-Joachim Schulze

IPC: H01L29/417 ,  H01L21/762 ,  H01L29/861 ,  H01L29/16 ,  H01L29/66 ,  H01L21/764 ,  H01L29/872 ,  H01L21/74 ,  H01L21/28 ,  H01L21/306 ,  H01L21/311 ,  H01L29/423 ,  H01L29/78 ,  H01L21/3105

Abstract: A semiconductor device includes a first epitaxial layer, a second epitaxial layer disposed below the first epitaxial layer, a conductive layer disposed below and directly contacting the second epitaxial layer, and a plurality of spacers disposed between the second epitaxial layer and the conductive layer. The conductive layer includes a metal. The plurality of spacers include a bulk semiconductor material.

公开(公告)号：US10802404B2

公开(公告)日：2020-10-13

申请号：US15919989

申请日：2018-03-13

Applicant: Infineon Technologies AG

Inventor： Joerg Ortner ,  Iris Moder ,  Ingo Muri

IPC: G03F7/20 ,  G03F1/00 ,  G03F1/42

Abstract: An exposure method includes projecting a reticle pattern into a first exposure field of a photoresist layer, wherein the reticle pattern includes first and second line patterns on opposite edges of the reticle pattern and wherein at least the first line pattern includes an end section through which light flux decreases outwards. The reticle pattern is further projected into a second exposure field of the photoresist layer, wherein a first tapering projection zone of the end section of the first line pattern in the second exposure field overlaps a projection area of the second line pattern in the first exposure field.

公开(公告)号：US20200168449A1

公开(公告)日：2020-05-28

申请号：US16677801

申请日：2019-11-08

Applicant: Infineon Technologies AG

Inventor： Sophia Friedler ,  Bernhard Goller ,  Iris Moder ,  Ingo Muri

IPC: H01L21/02 ,  H01L21/465 ,  H01L21/8258

Abstract: A method includes: in a semiconductor wafer including a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a first surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10−2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer.