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公开(公告)号：US20170133359A1
公开(公告)日：2017-05-11
申请号：US15415018
申请日：2017-01-25
Applicant: Micron Technology, Inc.
Inventor： Shizhong Mei , Victor Wong , Jeffrey P. Wright
IPC: H01L25/18 , H01L23/00 , H01L23/538 , H01L23/528 , H01L23/48 , H01L25/00
CPC classification number: H01L25/18 , H01L23/481 , H01L23/5286 , H01L23/5383 , H01L23/5384 , H01L24/05 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/18 , H01L25/50 , H01L2224/05025 , H01L2224/08235 , H01L2224/13024 , H01L2224/13025 , H01L2224/131 , H01L2224/16141 , H01L2224/16146 , H01L2224/16235 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06544 , H01L2225/06565 , H01L2225/06582 , H01L2225/06589 , H01L2924/1431 , H01L2924/1434 , H01L2924/014
Abstract: Semiconductor devices having modified current distribution and methods of forming the same are described herein. As an example, a memory die in contact with a logic die can be configured to draw a sum amount of current from a current source. The memory die can include a plurality of through-substrate vias (TSVs) formed in the memory die and configured to provide the sum amount of current to the memory die from the current source. The memory die can include at least two interconnection contacts associated with a first TSV closer to the current source that are not connected. The memory die can include an electrical connection between at least two interconnection contacts associated with a second TSV that is further in distance from the current source than the first TSV.
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公开(公告)号：US20160133310A1
公开(公告)日：2016-05-12
申请号：US14539331
申请日：2014-11-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Alan J. Wilson , Jeffrey P. Wright
IPC: G11C11/408 , G11C11/4076 , G11C16/06 , G11C11/4093
CPC classification number: G11C7/20 , G11C5/063 , G11C7/22 , G11C11/4072 , G11C11/4076 , G11C11/4093 , G11C16/06 , G11C16/20 , G11C17/18 , G11C29/021 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/14 , G11C29/46 , G11C29/70
Abstract: Memory die can be stacked to form a three-dimensional integrated circuit. For example, through-silicon vias (TSVs) can permit signals to pass vertically through the three-dimensional integrated circuit. Disclosed herein are apparatuses and methods to perform post package trimming of memory die, which advantageously permits the memory die to be trimmed after the memory die is stacked, such that test and trimming characteristics are relatively close to that which will be actually be encountered.
Abstract translation: 存储芯片可堆叠形成三维集成电路。 例如，硅通孔（TSV）可以允许信号垂直穿过三维集成电路。 这里公开了用于执行存储管芯的后封装修整的装置和方法，其有利地允许在存储器管芯堆叠之后对存储管芯进行修整，使得测试和修整特性相对接近将实际遇到的特性。
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公开(公告)号：US20150302907A1
公开(公告)日：2015-10-22
申请号：US14254378
申请日：2014-04-16
Applicant: Micron Technology, Inc.
Inventor： Mark K. Hadrick , Jeffrey P. Wright , Victor Wong , Simon J. Lovett , Donald M. Morgan , William F. Jones , Sujeet Ayyapureddi , Dean D. Gans , Jongtae Kwak
CPC classification number: G11C7/22 , G11C7/1009 , G11C7/1042 , G11C8/12 , G11C2207/229
Abstract: Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.
Abstract translation: 本文公开了用于实现屏蔽写入命令的装置和方法。 示例性装置可以包括存储体，局部缓冲电路和地址控制电路。 本地缓冲电路可以与存储体相关联。 地址控制电路可以耦合到存储体并被配置为接收命令和与命令相关联的地址。 地址控制电路可以包括被配置为存储地址的全局缓冲电路。 地址控制电路还可以被配置为至少部分地基于写等待时间来延迟使用多个命令路径之一的命令，并且将存储在全局缓冲器电路中的地址提供给要存储的本地缓冲器电路 其中。
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公开(公告)号：US20240125851A1
公开(公告)日：2024-04-18
申请号：US18047386
申请日：2022-10-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kenneth M. Curewitz , Jaime Cummins , John D. Porter , Bryce D. Cook , Jeffrey P. Wright
IPC: G01R31/319 , G01R31/3185
CPC classification number: G01R31/31907 , G01R31/318594 , G01R31/318597
Abstract: A memory controller and a physical interface layer may accommodate multiple memory types. In some examples, the memory controller and/or PHY may include a register that includes operating parameters for multiple operating modes. Different operating modes may be compatible with different memory types. In some examples, the memory controller and physical interface may be included in a system for testing multiple memory types. The system may provide multiple interfaces for communicating with the memory. The different communication types may be used for performing different tests and/or simulating different types of devices that may utilize the memory.
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公开(公告)号：US20230004507A1
公开(公告)日：2023-01-05
申请号：US17864023
申请日：2022-07-13
Applicant: Micron Technology, Inc.
Inventor： Robert Nasry Hasbun , Timothy M. Hollis , Jeffrey P. Wright , Dean D. Gans
IPC: G06F13/16 , G06F13/40 , G11C5/06 , G11C5/02 , G06F13/42 , G11C11/4093 , G11C7/10 , G11C11/4096 , G11C5/04
Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.
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Patent Agency Ranking
公开(公告)号：US20210105161A1
公开(公告)日：2021-04-08
申请号：US17123990
申请日：2020-12-16
Applicant: Micron Technology, Inc.
Inventor： Robert Nasry Hasbun , Timothy M. Hollis , Jeffrey P. Wright , Dean D. Gans
Abstract: Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.
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公开(公告)号：US10811066B2
公开(公告)日：2020-10-20
申请号：US16190627
申请日：2018-11-14
Applicant: MICRON TECHNOLOGY, INC.
Inventor： William F. Jones , Jeffrey P. Wright
IPC: G11C8/00 , G11C8/10 , G11C11/406 , G11C11/408 , G11C17/16 , G11C17/18 , G11C29/00
Abstract: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.
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公开(公告)号：US10725913B2
公开(公告)日：2020-07-28
申请号：US15977808
申请日：2018-05-11
Applicant: Micron Technology, Inc.
Inventor： Robert Nasry Hasbun , Timothy M. Hollis , Jeffrey P. Wright , Dean D. Gans
IPC: G06F13/16 , G06F12/0806 , H04L5/00 , H04L27/14
Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.
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公开(公告)号：US20190273052A1
公开(公告)日：2019-09-05
申请号：US16416210
申请日：2019-05-18
Applicant: Micron Technology, Inc.
Inventor： James E. Davis , Kevin G. Duesman , Jeffrey P. Wright , Warren L. Boyer
IPC: H01L23/60 , H01L23/00 , H01L23/538 , H01L25/04
Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements, and a plated pad electrically coupling at least a part of the first contact pad to at least a part of the second contact pad. The substrate includes a substrate contact electrically coupled to the plated pad on the die.
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公开(公告)号：US20190228810A1
公开(公告)日：2019-07-25
申请号：US16375764
申请日：2019-04-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： William F. Jones , Jeffrey P. Wright
IPC: G11C8/10 , G11C29/00 , G11C11/406 , G11C17/16 , G11C11/408 , G11C17/18
Abstract: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.
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