公开(公告)号：US20150170756A1

公开(公告)日：2015-06-18

申请号：US14632556

申请日：2015-02-26

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Mark Helm ,  Pranav Kalavade ,  Charan Srinivasan

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459

Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first pass of programming, a first bias voltage value to a source select gate to isolate memory cells from a source, applying a programming voltage to an access line of a page of the memory cells during the first pass of programming, and applying a second bias voltage value to the source select gate to isolate the memory cells from the source during a second pass of programming. Further devices, systems, and methods are disclosed.

Abstract translation: 一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。 一种这样的方法可以包括在编程的第一次通过期间将第一偏置电压值应用于源极选择栅极以将存储器单元与源极隔离，在第一次处理期间将编程电压施加到存储器单元的页面的访问线 编程的通过，以及在源选择栅极施加第二偏置电压值以在第二次编程期间隔离存储器单元与源极。 公开了其它装置，系统和方法。

公开(公告)号：US20140313825A1

公开(公告)日：2014-10-23

申请号：US14320068

申请日：2014-06-30

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Pranav Kalavade ,  Doyle Rivers

IPC: G11C16/12 ,  G11C16/04

CPC classification number: G11C16/12 ,  G11C16/04 ,  G11C16/0433

Abstract: Some embodiments include apparatus, systems, and methods that operate to apply a first value of a drain select gate voltage during a first portion of a programming time period associated with programming a plurality of memory cells, and to apply a second value of the drain select gate voltage different from the first value during a second, subsequent portion of the programming time period. The drain select gate voltage may be changed between groups of programming pulses in a single programming cycle. The first and second portions may be determined according to the number of applied programming pulses, the number of memory cells that have been completely programmed, and/or other conditions. Additional apparatus, systems, and methods are disclosed.

Abstract translation: 一些实施例包括在与编程多个存储器单元相关联的编程时间周期的第一部分期间操作以施加漏极选择栅极电压的第一值的装置，系统和方法，以及施加漏极选择的第二值 在第二编程时间段的后续部分中，栅极电压与第一值不同。 漏极选择栅极电压可以在单个编程周期中的编程脉冲组之间改变。 第一和第二部分可以根据应用的编程脉冲的数量，已经完全编程的存储器单元的数量和/或其他条件来确定。 公开了附加装置，系统和方法。

公开(公告)号：US11182074B2

公开(公告)日：2021-11-23

申请号：US16401089

申请日：2019-05-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Toru Tanzawa

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G11C16/26 ,  G11C16/30 ,  G11C8/12 ,  G11C11/56 ,  G11C16/08 ,  G11C13/00 ,  G11C16/04

Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

公开(公告)号：US20200066350A1

公开(公告)日：2020-02-27

申请号：US16655826

申请日：2019-10-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Violante Moschiano ,  Purval S. Sule ,  Han Liu ,  Andrea D'Alessandro ,  Pranav Kalavade ,  Han Zhao ,  Shantanu Rajwade

IPC: G11C16/12 ,  G11C16/34 ,  G11C11/4074 ,  G11C5/06 ,  G11C16/04

Abstract: Memories having a controller configured to perform methods during programming operations including applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.

公开(公告)号：US20180373451A1

公开(公告)日：2018-12-27

申请号：US16117348

申请日：2018-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/24 ,  G11C16/04 ,  G06F13/28 ,  G06F12/0846 ,  G06F12/0804

CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0665 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0804 ,  G06F12/0846 ,  G06F13/28 ,  G06F2212/2022 ,  G06F2212/224 ,  G06F2212/461 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  Y02D10/14

Abstract: Methods for programming sense flags may include programming memory cells coupled to first data lines in a main memory array, and programming memory cells coupled to second data lines in the main memory array while programming memory cells coupled to data lines in a flag memory array with flag data indicative of the memory cells coupled to the second data lines being programmed. Methods for sensing flags may include performing a sense operation on memory cells coupled to first data lines of a main memory array and memory cells coupled to data lines of a flag memory array, and determining a program indication of memory cells coupled to second data lines of the main memory array from the sense operation performed on the memory cells coupled to the data lines of the flag memory array.

公开(公告)号：US09977622B1

公开(公告)日：2018-05-22

申请号：US15359306

申请日：2016-11-22

Applicant: Micron Technology, Inc.

Inventor： Pranav Kalavade ,  Shantanu R. Rajwade

IPC: G11C16/04 ,  G06F3/06 ,  G11C16/10

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0679 ,  G11C7/1084 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/32

Abstract: Apparatuses and methods for performing buffer operations in memory are provided. One example method can include storing second page data and third page data on a buffer while programming first page data during a first pass programming operation and programming the second page data and the third page data from the buffer to the array of memory cells during a second pass programming operation.

公开(公告)号：US09576674B2

公开(公告)日：2017-02-21

申请号：US14663179

申请日：2015-03-19

Applicant: Micron Technology, Inc.

Inventor： Matthew Goldman ,  Pranav Kalavade ,  Uday Chandrasekhar ,  Mark A. Helm

IPC: G11C16/06 ,  G11C16/28 ,  G11C16/26 ,  G11C16/34 ,  G06F12/08 ,  G11C16/04

CPC classification number: G11C16/28 ,  G06F12/0875 ,  G06F2212/452 ,  G11C16/04 ,  G11C16/26 ,  G11C16/3427

Abstract: This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data.

Abstract translation: 本公开涉及存储器单元感测。 一种或多种方法包括确定耦合到第一数据线的第一存储器单元的数据状态，确定耦合到第三数据线的第三存储器单元的数据状态，传送第一和第三数据线中的至少一个的确定数据 存储单元连接到与第二存储器单元耦合的第二数据线相对应的数据线控制单元，第二数据线与第一数据线和第三数据线相邻，并且确定第二存储器单元的数据状态 至少部分地基于所转移的确定的数据。

公开(公告)号：US09396791B2

公开(公告)日：2016-07-19

申请号：US14334946

申请日：2014-07-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shyam Sunder Raghunathan ,  Pranav Kalavade ,  Krishna K. Parat ,  Charan Srinivasan

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3427

Abstract: Memories and methods for programming memories with multi-level pass signals are provided. One method includes programming cells of the memory selected to be programmed to a particular target data state of the memory, using program disturb to program cells of the memory selected to be programmed to target data states that are lower than the particular target data state while programming cells of the memory selected to be programmed to the particular target data state, and boosting a channel voltage for cells of the memory selected to be programmed to the target data states that are lower than the particular target data state. Boosting may include using a multi-step pass signal.

Abstract translation: 提供了用于编程具有多级通过信号的存储器的存储器和方法。 一种方法包括将选择要编程的存储器的单元编程为存储器的特定目标数据状态，使用程序干扰来编程选择要编程的存储器的单元，以在编程期间将目标数据状态低于特定目标数据状态 将存储器的单元选择为被编程到特定目标数据状态，以及将选择要编程的存储器的单元的通道电压提升到低于特定目标数据状态的目标数据状态。 升压可能包括使用多步通过信号。

公开(公告)号：US09230666B2

公开(公告)日：2016-01-05

申请号：US14320068

申请日：2014-06-30

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Pranav Kalavade ,  Doyle Rivers

IPC: G11C7/00 ,  G11C16/12 ,  G11C16/04

CPC classification number: G11C16/12 ,  G11C16/04 ,  G11C16/0433

Abstract: Some embodiments include apparatus, systems, and methods that operate to apply a first value of a drain select gate voltage during a first portion of a programming time period associated with programming a plurality of memory cells, and to apply a second value of the drain select gate voltage different from the first value during a second, subsequent portion of the programming time period. The drain select gate voltage may be changed between groups of programming pulses in a single programming cycle. The first and second portions may be determined according to the number of applied programming pulses, the number of memory cells that have been completely programmed, and/or other conditions. Additional apparatus, systems, and methods are disclosed.

Abstract translation: 一些实施例包括在与编程多个存储器单元相关联的编程时间周期的第一部分期间操作以施加漏极选择栅极电压的第一值的装置，系统和方法，以及施加漏极选择的第二值 在第二编程时间段的后续部分中，栅极电压与第一值不同。 漏极选择栅极电压可以在单个编程周期中的编程脉冲组之间改变。 第一和第二部分可以根据应用的编程脉冲的数量，已经完全编程的存储器单元的数量和/或其他条件来确定。 公开了附加装置，系统和方法。

公开(公告)号：US20150363313A1

公开(公告)日：2015-12-17

申请号：US14833175

申请日：2015-08-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

IPC: G06F12/08 ,  G06F13/28 ,  G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0665 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0804 ,  G06F12/0846 ,  G06F13/28 ,  G06F2212/2022 ,  G06F2212/224 ,  G06F2212/461 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  Y02D10/14

Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.

Abstract translation: 公开了存储器件，用于编程感测标志的方法，用于感测标志的方法和存储器系统。 在一个这样的存储器件中，标志存储器单元阵列的奇数位线与短路连接到动态数据高速缓存。 标记存储单元阵列的偶数位线与动态数据高速缓存断开连接。 当读取主存储单元阵列的偶数页时，同时读取包括标志数据的奇数标志存储单元，以便可以确定主存储单元阵列的奇数页是否已被编程。 如果标志数据指示奇数页未被编程，则可以调整阈值电压窗口以确定感测到的偶数存储单元页的状态。