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    Devices and operation methods for configuring data strobe signal in memory device
    21.
    发明授权
    Devices and operation methods for configuring data strobe signal in memory device 有权

    公开(公告)号：US09652228B2

    公开(公告)日：2017-05-16

    申请号：US14677321

    申请日：2015-04-02

    Applicant: Macronix International Co., Ltd.

    Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chang-Ting Chen

    IPC: G06F12/00 ,  G06F9/00

    CPC classification number: G06F9/00 ,  G06F1/12 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C16/00 ,  G11C29/023

    Abstract: A non-volatile memory device includes a memory core storing data to be output from the memory core according to an external clock signal, an input buffer receiving the external clock signal and providing an input clock signal, and a synchronization circuit including a delay circuit and configured to receive the input clock signal, provide an output clock signal, and synchronize the output clock signal to the external clock signal. The device further includes a data strobe output buffer receiving the output clock signal and providing a data strobe signal having a signal delay configurable relative to the external clock signal, a clocked circuit element receiving the data and the output clock signal and outputting the data in synchronism with the output clock signal, and a delay control circuit providing a delay control signal to the delay circuit to modify the signal delay of the data strobe signal.

    DECODE SWITCH AND METHOD FOR CONTROLLING DECODE SWITCH
    24.
    发明申请
    DECODE SWITCH AND METHOD FOR CONTROLLING DECODE SWITCH 有权
    解码开关和控制解码开关的方法

    公开(公告)号：US20160204697A1

    公开(公告)日：2016-07-14

    申请号：US14693565

    申请日：2015-04-22

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Yi-Fan Chang ,  Chun-Yi Lee ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    IPC: H02M3/10 ,  H03K17/30

    CPC classification number: H03K17/007 ,  G11C8/00 ,  G11C8/10 ,  H03K2217/0036

    Abstract: A decode switch and a method for controlling a decode switch are provided. The decode switch includes a power source providing a first voltage, a source capacitance coupled to the power source, and a target capacitance coupled to the power source. The power source charges the source capacitance to the first voltage. The source capacitance is connected to the target capacitance and the source capacitance charges the target capacitance to a second voltage. The power source charges the target capacitance from the second voltage to the first voltage.

    Abstract translation: 提供了解码开关和用于控制解码开关的方法。 解码开关包括提供第一电压的电源，耦合到电源的源电容和耦合到电源的目标电容。 电源将源电容充电到第一电压。 源电容连接到目标电容，源电容将目标电容充电到第二电压。 电源将目标电容从第二电压充电到第一电压。

    Retention logic for non-volatile memory
    26.
    发明授权
    Retention logic for non-volatile memory 有权
    非易失性存储器的保留逻辑

    公开(公告)号：US09147501B2

    公开(公告)日：2015-09-29

    申请号：US13903574

    申请日：2013-05-28

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chun-Hsiung Hung ,  Nai-Ping Kuo ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Yu-Chen Wang

    IPC: G11C29/00 ,  G11C29/12 ,  G11C16/34

    CPC classification number: G11C16/34 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/349 ,  G11C29/12005 ,  G11C29/50004 ,  G11C29/50016

    Abstract: An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state characterized by a minimum threshold exceeding a selected read bias. A controller includes a stand-by mode, a write mode and a read mode. Retention check logic executes on power-up, or during the stand-by mode, to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells.

    Abstract translation: 集成电路存储器件包括非易失性电荷捕获存储器单元的阵列，其被配置为使用阈值状态将数据值存储在阵列中的存储器单元中，所述阈值状态包括以超过所选择的读偏差的最小阈值为特征的较高阈值状态。 控制器包括待机模式，写入模式和读取模式。 保持检查逻辑在上电或待机模式下执行，以识别在阈值保持检查失败的较高阈值状态下的存储器单元。 此外，提供逻辑以重新编程所识别的存储器单元。

    MEMORY DEVICE AND READ OPERATION METHOD THEREOF
    28.
    发明申请
    MEMORY DEVICE AND READ OPERATION METHOD THEREOF 有权
    存储器件及其读取操作方法

    公开(公告)号：US20150023120A1

    公开(公告)日：2015-01-22

    申请号：US14506768

    申请日：2014-10-06

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Su-Chueh Lo ,  Ken-Hui Chen ,  Kuen-Long Chang

    IPC: G11C7/10 ,  G11C7/12 ,  G11C7/06

    CPC classification number: G11C7/1048 ,  G11C7/06 ,  G11C7/08 ,  G11C7/106 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002

    Abstract: A read operation for a memory device is provided. A selected word line, first and second global bit line groups and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit line groups are kept precharged.

    Abstract translation: 提供了存储器件的读取操作。 选择的字线，第一和第二全局位线组和所选择的第一位线组被预先充电。 流过所选字线的第一单元电流，产生第一和所选择的第一位线组。 产生流过第二全局位线组的第一参考电流。 基于第一单元电流和第一参考电流来读取前​​半页数据。 所选择的字线，第一和第二全局位线组保持预充电。

    METHOD AND APPARATUS FOR LEAKAGE SUPPRESSION IN FLASH MEMORY IN RESPONSE TO EXTERNAL COMMANDS
    29.
    发明申请
    METHOD AND APPARATUS FOR LEAKAGE SUPPRESSION IN FLASH MEMORY IN RESPONSE TO EXTERNAL COMMANDS 有权
    FLASH存储器中对外部命令的泄漏抑制方法和装置

    公开(公告)号：US20140219026A1

    公开(公告)日：2014-08-07

    申请号：US14249270

    申请日：2014-04-09

    Applicant: Macronix International Co., Ltd.

    Inventor： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

    IPC: G11C16/34

    CPC classification number: G11C16/3409 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/14

    Abstract: Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.

    Abstract translation: 本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。 在一个实施例中，闪存器件包括包括多个存储单元块的存储器阵列。 该设备还包括用于从存储设备外部的源接收命令的命令接口。 该装置还包括控制器，其包括响应于该命令执行泄漏抑制处理的逻辑。 泄漏抑制处理包括执行软程序操作以增加给定的存储单元块中的一个或多个过擦除存储器单元的阈值电压并建立擦除状态。

    Apparatus and method to tolerate floating input pin for input buffer
    30.
    发明授权
    Apparatus and method to tolerate floating input pin for input buffer 有权
    允许输入缓冲器的浮动输入引脚的装置和方法

    公开(公告)号：US08723563B2

    公开(公告)日：2014-05-13

    申请号：US13845576

    申请日：2013-03-18

    Applicant: Macronix International Co., Ltd.

    Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Nai-Ping Kuo ,  Ming-Chih Hsieh

    IPC: H03K3/00

    CPC classification number: H03K3/00 ,  H03K19/0002 ,  H03K19/09425

    Abstract: An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch.

    Abstract translation: 集成电路装置包括适于从内部或外部驱动器接收信号的焊盘以及包括耦合到焊盘的输入端的输入缓冲电路。 输入缓冲器电路包括具有控制端子的传输晶体管，连接到焊盘的第一导电端子和连接到第一电压的第二导电端子。 输入缓冲电路还包括具有电耦合到传输晶体管的控制端的端子的锁存器。 所述输入缓冲器电路还包括耦合到所述锁存器的电路，所述电路包括反馈晶体管，所述反馈晶体管具有电耦合到所述焊盘的控制端子，电耦合到第二电压的第一导电端子以及耦合到所述锁存器的第二导电端子。

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