Methods for isolating portions of a loop of pitch-multiplied material and related structures
    23.
    发明授权
    Methods for isolating portions of a loop of pitch-multiplied material and related structures 有权
    隔离倍增材料和相关结构环的部分的方法

    公开(公告)号:US08932960B2

    公开(公告)日:2015-01-13

    申请号:US13777803

    申请日:2013-02-26

    Inventor: Luan C. Tran

    Abstract: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.

    Abstract translation: 半导体材料的连续环路的不同部分彼此电隔离。 在一些实施例中,环路的端部与环路的中间部分电隔离。 在一些实施例中,具有在其端部连接在一起的两个腿的半导体材料的环通过间距倍增过程形成,其中间隔物的环形成在心轴的侧壁上。 去除心轴并且将一块掩模材料覆盖在间隔环的至少一端上。 在一些实施例中,掩模材料块覆盖间隔环的每一端。 由间隔物和块限定的图案被转移到半导体材料层。 这些块将所有环路电连接在一起。 沿循环的每条腿形成选择门。 这些块作为源/排水沟。 选择门被偏置在关闭状态以防止电流从环路的中部流向块,从而将中间部分与环的端部电隔离,并且还将环路的不同的腿与每个 其他。

    Memory having a continuous channel
    25.
    发明授权

    公开(公告)号:US12279420B2

    公开(公告)日:2025-04-15

    申请号:US17723716

    申请日:2022-04-19

    Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.

    Memory Array and Methods Used in Forming a Memory Array

    公开(公告)号:US20240244837A1

    公开(公告)日:2024-07-18

    申请号:US18433863

    申请日:2024-02-06

    Abstract: A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.

    Integrated Structures and Methods of Forming Integrated Structures

    公开(公告)号:US20200176471A1

    公开(公告)日:2020-06-04

    申请号:US16783981

    申请日:2020-02-06

    Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

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