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    Trenched DMOS transistor having thick field oxide in termination region
    21.
    发明授权
    Trenched DMOS transistor having thick field oxide in termination region 失效
    在端接区域具有厚场氧化物的沟槽DMOS晶体管

    公开(公告)号：US5578851A

    公开(公告)日：1996-11-26

    申请号：US625639

    申请日：1996-03-29

    申请人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Yueh-Se Ho ,  King Owyang

    发明人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Yueh-Se Ho ,  King Owyang

    IPC分类号： H01L21/316 ,  H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/407 ,  H01L29/404 ,  H01L29/7813

    摘要： A trenched DMOS transistor is fabricated using seven masking steps. One masking step defines both the P+ deep body regions and the active portions of the transistor which are masked using a LOCOS process. A second masking step defines the insulating oxide in the termination region. The insulating (oxide) layer in the termination region is thus thicker than in the active region of the transistor, thereby improving process control and reducing substrate contamination during processing. Additionally, the thicker field oxide in the termination region improves electric field distribution so that avalanche breakdown occurs in the cell (active) region rather than in the termination region, and thus breakdown voltage behavior is more stable and predictable.

    摘要翻译： 使用七个掩模步骤制造出沟槽的DMOS晶体管。 一个掩模步骤限定使用LOCOS工艺掩蔽的P +深体区域和晶体管的有源部分。 第二掩蔽步骤限定了端接区域中的绝缘氧化物。 因此，端接区域中的绝缘（氧化物）层比晶体管的有源区域厚，从而改善了处理过程中的工艺控制和减少了衬底污染。 此外，端接区域中较厚的场氧化物改善了电场分布，使得雪崩击穿发生在电池（有源）区而不是终端区，因此击穿电压行为更稳定和可预测。

    Trenched DMOS transistor fabrication using six masks
    22.
    发明授权
    Trenched DMOS transistor fabrication using six masks 失效
    使用六个掩模制成DMOS晶体管

    公开(公告)号：US5316959A

    公开(公告)日：1994-05-31

    申请号：US928909

    申请日：1992-08-12

    申请人： Sze-Hon Kwan ,  Fwu-Iuan Hshieh ,  Mike F. Chang ,  Yueh-Se Ho ,  King Owyang

    发明人： Sze-Hon Kwan ,  Fwu-Iuan Hshieh ,  Mike F. Chang ,  Yueh-Se Ho ,  King Owyang

    IPC分类号： H01L21/265 ,  H01L21/316 ,  H01L21/318 ,  H01L21/336 ,  H01L21/76 ,  H01L29/06 ,  H01L29/78

    CPC分类号： H01L29/0619 ,  H01L29/7813

    摘要： A trenched DMOS transistor is fabricated using six masking steps. One masking step defines both the P+ regions and the active portions of the transistor which are masked using a LOCOS process. The LOCOS process also eliminates the poly stringer problem present in prior art structures by reducing the oxide step height. A transistor termination structure includes several field rings, each set of adjacent field rings separated by an insulated trench, thus allowing the field rings to be spaced very close together. The field rings and trenches are fabricated in the same steps as are corresponding portions of the active transistor.

    摘要翻译： 使用六个掩模步骤制造沟槽DMOS晶体管。 一个掩模步骤限定使用LOCOS工艺掩蔽的P +区域和晶体管的有源部分。 LOCOS工艺还通过降低氧化物台阶高度来消除现有技术结构中存在的多边形问题。 晶体管端接结构包括几个场环，每组相邻的场环由绝缘沟槽隔开，从而允许场环非常靠近在一起。 场环和沟槽以与有源晶体管的对应部分相同的步骤制造。