公开(公告)号：US07772701B2

公开(公告)日：2010-08-10

申请号：US11422769

申请日：2006-06-07

申请人： Chih-Hsiang Yao ,  Tai-Chun Huang ,  Mong-Song Liang

发明人： Chih-Hsiang Yao ,  Tai-Chun Huang ,  Mong-Song Liang

IPC分类号： H01L23/48 ,  H01L29/40

CPC分类号： H01L23/522 ,  H01L23/481 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

摘要： An improved integrated circuit structure and method of making the same is provided. The integrated circuit structure comprises a substrate, the substrate having a top surface and a bottom surface. The top surface has a circuit device formed thereon. The structure includes a plurality of metallization layers, a bonding structure formed over the bottom surface and a conductive interconnect structure formed through said substrate.

摘要翻译： 提供了一种改进的集成电路结构及其制造方法。 集成电路结构包括基板，该基板具有顶表面和底表面。 顶表面上形成有电路装置。 该结构包括多个金属化层，形成在底表面上的接合结构和通过所述衬底形成的导电互连结构。

公开(公告)号：US20060246686A1

公开(公告)日：2006-11-02

申请号：US10908142

申请日：2005-04-28

申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Chin-Chiu Hsia ,  Mong-Song Liang

发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Chin-Chiu Hsia ,  Mong-Song Liang

IPC分类号： H01L21/30 ,  H01L21/4763 ,  H01L21/46

CPC分类号： H01L24/48 ,  H01L21/76804 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2224/45099

摘要： Described are methods and structures for mitigating the effects of mechanical stresses placed on the layers of semiconductor devices, and specifically disclosed are methods and structures for mitigating the diminished chemical bonds between etch-stop layers and other semiconductor device layers. The disclosed methods and structures use different structures and/or processes for some of the etch-stop layers in a device.

摘要翻译： 描述了用于减轻放置在半导体器件层上的机械应力的影响的方法和结构，并且具体公开了用于减轻蚀刻停止层和其它半导体器件层之间减少的化学键的方法和结构。 所公开的方法和结构对于装置中的一些蚀刻停止层使用不同的结构和/或工艺。

公开(公告)号：US06927498B2

公开(公告)日：2005-08-09

申请号：US10716682

申请日：2003-11-19

申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Ching-Hua Hsieh

发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Ching-Hua Hsieh

IPC分类号： H01L23/485 ,  H01L23/29

CPC分类号： H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05093 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/48

摘要： A bond pad for a flip chip package. The bond pad is suitable for an integrated circuit chip. A plurality of slots are designed in the bond pad. Each of the slots extends along a direction which is perpendicular to a radial direction from the center of the bond pad. The bond pad is deposed at the corner of the integrated circuit chip.

公开(公告)号：US20050133241A1

公开(公告)日：2005-06-23

申请号：US10742240

申请日：2003-12-18

申请人： Kuan-Shou Chi ,  Tai-Chun Huang ,  Chih-Hsiang Yao

发明人： Kuan-Shou Chi ,  Tai-Chun Huang ,  Chih-Hsiang Yao

IPC分类号： H01L21/58 ,  H01L21/60 ,  H01L23/02 ,  H05K3/30

CPC分类号： H01L24/83 ,  H01L24/29 ,  H01L2224/2919 ,  H01L2224/45124 ,  H01L2224/83121 ,  H01L2224/83191 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/351 ,  Y10T29/4913 ,  Y10T29/49133 ,  H01L2924/00 ,  H01L2224/48

摘要： A chip orientation and attachment method is disclosed which eliminates or substantially reduces chip damage caused by thermal stress induced by application of a molding compound to the chip and substrate. The chip is attached to the substrate in such a manner that at least one of the following conditions exists: the chip diagonal and the substrate diagonal are in non-aligned relationship, and/or the chip edges are non-parallel with respect to the substrate edges, and/or the chip center is in non-overlapping relationship with respect to the substrate center. The invention includes chip package structures fabricated according to the chip orientation and attachment method.

摘要翻译： 公开了一种芯片取向和附接方法，其消除或基本上减少由于将模塑料施加到芯片和基板而引起的热应力引起的芯片损伤。 芯片以这样的方式附接到基板，使得存在以下条件中的至少一个：芯片对角线和基板对角线处于非对准关系，和/或芯片边缘相对于基板不平行 边缘和/或芯片中心相对于基板中心处于非重叠关系。 本发明包括根据芯片取向和附着方法制造的芯片封装结构。

公开(公告)号：US20050127529A1

公开(公告)日：2005-06-16

申请号：US10731983

申请日：2003-12-10

申请人： Tai-Chun Huang ,  Chih-Hsiang Yao

发明人： Tai-Chun Huang ,  Chih-Hsiang Yao

IPC分类号： H01L21/44 ,  H01L23/48 ,  H01L23/485 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/48463 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00

摘要： A structure for reinforcing or anchoring a bond pad on a chip. The structure includes a bonding pad provided in a dielectric layer, at least one conductive layer provided beneath and in electrical contact with the bonding pad, and at least one parallel-interconnect anchor structure provided in contact with the bonding pad and the conductive layer. The anchor structure or structures prevent the bonding pad from exerting excessive force against the dielectric layer and cracking the dielectric layer when the chip is subjected to physical testing. The bonding pad may have truncated or curved corners, for example.

摘要翻译： 用于加强或固定芯片上的焊盘的结构。 该结构包括设置在电介质层中的接合焊盘，设置在接合焊盘下方并与接合焊盘电接触的至少一个导电层以及与接合焊盘和导电层接触地设置的至少一个平行互连锚固结构。 锚定结构或结构防止接合垫在芯片进行物理测试时对电介质层施加过大的力并破坏电介质层。 例如，接合焊盘可以具有截头或弯曲的拐角。

公开(公告)号：US07777338B2

公开(公告)日：2010-08-17

申请号：US10940504

申请日：2004-09-13

申请人： Chih-Hsiang Yao ,  Tai-Chun Huang ,  Kuan-Shou Chi ,  Chih-Cherng Jeng ,  Ming-Shuoh Liang ,  Wen-Kai Wan ,  Chin-Chiu Hsia

发明人： Chih-Hsiang Yao ,  Tai-Chun Huang ,  Kuan-Shou Chi ,  Chih-Cherng Jeng ,  Ming-Shuoh Liang ,  Wen-Kai Wan ,  Chin-Chiu Hsia

IPC分类号： H01L23/48

CPC分类号： H01L21/78 ,  B28D5/0011 ,  H01L21/76224 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A seal ring structure is disclosed for protecting a core circuit region of an integrated circuit chip. The seal ring structure includes a metallization layer, having a bridge sublevel and a plug sublevel. An upper-level bridge is formed on the bridge sublevel at a predetermined location between a peripheral edge of the integrated circuit chip and the core circuit region. A lower-level bridge is formed on the plug sublevel in substantial alignment with the upper-level bridge, wherein the lower-level bridge has a width substantially the same as that of the upper-level bridge.

摘要翻译： 公开了用于保护集成电路芯片的核心电路区域的密封环结构。 密封圈结构包括具有桥接子层和插塞子层的金属化层。 在集成电路芯片的外围边缘和核心电路区域之间的预定位置处，在桥接子层上形成上层电桥。 在与上层桥接器基本对准的插头子级上形成有较低级别的桥，其中下级桥具有与上级桥基本相同的宽度。

公开(公告)号：US07592710B2

公开(公告)日：2009-09-22

申请号：US11409297

申请日：2006-04-21

申请人： Chin-Chiu Hsia ,  Chih-Hsiang Yao ,  Tai-Chun Huang ,  Chih-Tang Peng

发明人： Chin-Chiu Hsia ,  Chih-Hsiang Yao ,  Tai-Chun Huang ,  Chih-Tang Peng

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/10 ,  H01L29/739 ,  H01L29/73 ,  H01L29/74

CPC分类号： H01L24/05 ,  H01L24/45 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48666 ,  H01L2224/48681 ,  H01L2224/48684 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48766 ,  H01L2224/48784 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2224/48781 ,  H01L2924/00012

摘要： A bond pad structure of an integrated circuit is provided. The bond pad structure includes a conductive bond pad, a first dielectric layer underlying the bond pad, and an Mtop plate located in the first dielectric layer and underlying the bond pad. The Mtop plate is a solid conductive plate and is electrically coupled to the bond pad. The bond pad structure further includes a first passivation layer over the first dielectric layer wherein the first passivation layer has at least a portion under a middle portion of the bond pad. At least part of an active circuit is located under the bond pad.

摘要翻译： 提供集成电路的接合焊盘结构。 接合焊盘结构包括导电接合焊盘，接合焊盘下面的第一介电层和位于第一介电层中并位于接合焊盘下方的Mtop板。 Mtop板是固体导电板，并且电耦合到接合焊盘。 所述接合焊盘结构还包括在所述第一电介质层上的第一钝化层，其中所述第一钝化层具有在所述接合焊盘的中间部分下方的至少一部分。 有源电路的至少一部分位于接合焊盘下方。

公开(公告)号：US20070284747A1

公开(公告)日：2007-12-13

申请号：US11422769

申请日：2006-06-07

申请人： Chih-Hsiang Yao ,  Tai-Chun Huang ,  Mong-Song Liang

发明人： Chih-Hsiang Yao ,  Tai-Chun Huang ,  Mong-Song Liang

IPC分类号： H01L23/52

CPC分类号： H01L23/522 ,  H01L23/481 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

摘要： An improved integrated circuit structure and method of making the same is provided. The integrated circuit structure comprises a substrate, the substrate having a top surface and a bottom surface. The top surface has a circuit device formed thereon. The structure includes a plurality of metallization layers, a bonding structure formed over the bottom surface and a conductive interconnect structure formed through said substrate.

摘要翻译： 提供了一种改进的集成电路结构及其制造方法。 集成电路结构包括基板，该基板具有顶表面和底表面。 顶表面上形成有电路装置。 该结构包括多个金属化层，形成在底表面上的接合结构和通过所述衬底形成的导电互连结构。

公开(公告)号：US07265436B2

公开(公告)日：2007-09-04

申请号：US10780512

申请日：2004-02-17

申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi

发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi

IPC分类号： H01L23/544

CPC分类号： H01L23/564 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an improved seal ring structure is described. A continuous metal seal ring is formed along a perimeter of a die wherein the metal seal ring is parallel to the edges of the die and sloped at the corner of the die so as not to have a sharp corner and wherein the metal seal ring has a first width at the corners and a second width along the edges wherein the first width is wider than the second width.

摘要翻译： 描述形成改进的密封环结构的方法。 沿着模具的周边形成连续的金属密封环，其中金属密封环平行于模具的边缘并在模具的拐角处倾斜，以便不具有尖角，并且其中金属密封环具有 角部处的第一宽度和沿着边缘的第二宽度，其中第一宽度宽于第二宽度。

公开(公告)号：US20060091536A1

公开(公告)日：2006-05-04

申请号：US10979408

申请日：2004-11-02

申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Wen-Kai Wan

发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Wen-Kai Wan

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02125 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05076 ,  H01L2224/05083 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05576 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48799 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01077 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2924/00012

摘要： A bond pad structure for an integrated circuit chip has a stress-buffering layer between a top interconnection level metal layer and a bond pad layer to prevent damages to the bond pad structure from wafer probing and packaging impacts. The stress-buffering layer is a conductive material having a property selected from the group consisting of Young's modulus, hardness, strength and toughness greater than the top interconnection level metal layer or the bond pad layer. For improving adhesion and bonding strength, the lower portion of the stress-buffering layer may be modified as various forms of a ring, a mesh or interlocking-grid structures embedded in a passivation layer, alternatively, the stress-buffering layer may has openings filled with the bond pad layer.

摘要翻译： 用于集成电路芯片的接合焊盘结构在顶部互连级金属层和接合焊盘层之间具有应力缓冲层，以防止焊盘结构对晶片探测和封装冲击的损害。 应力缓冲层是具有选自杨氏模量，硬度，强度和韧性大于顶部互连级金属层或接合焊盘层的性质的导电材料。 为了提高附着力和粘结强度，应力缓冲层的下部可以被修改为嵌入钝化层中的各种形式的环，网或互锁网格结构，或者应力缓冲层可以具有开口 与焊垫层。